Data Sheet (CP80617004803AA)Table of ContentsFeatures Summary9Introduction9Platform10Processor Feature Details111.2.1 Supported Technologies11Interfaces111.3.1 System Memory Support111.3.2 PCI Express*121.3.3 Direct Media Interface (DMI)131.3.4 Platform Environment Control Interface (PECI)141.3.5 Intel® HD Graphics Controller141.3.6 Embedded DisplayPort* (eDP*)151.3.7 Intel® Flexible Display Interface (Intel® FDI)15Power Management Support151.4.1 Processor Core151.4.2 System151.4.3 Memory Controller161.4.4 PCI Express*161.4.5 DMI161.4.6 Integrated Graphics Controller16Thermal Management Support16Package16Terminology17Related Documents19Interfaces20System Memory Interface202.1.1 System Memory Technology Supported202-1 Supported SO-DIMM Module Configurations1202.1.2 System Memory Timing Support212.1.3 System Memory Organization Modes212-2 DDR3 System Memory Timing Support212-2 Intel Flex Memory Technology Operation222.1.4 Rules for Populating Memory Slots232.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)242.1.6 DRAM Clock Generation242.1.7 System Memory Pre-Charge Power Down Support Details24PCI Express Interface252.2.1 PCI Express Architecture252-4 PCI Express Layering Diagram252-5 Packet Flow through the Layers262.2.2 PCI Express Configuration Mechanism272.2.3 PCI Express Ports and Bifurcation272-6 PCI Express Related Register Structures in the Processor27DMI282.3.1 DMI Error Flow282.3.2 Processor/PCH Compatibility Assumptions282.3.3 DMI Link Down28Intel® HD Graphics Controller292.4.1 3D and Video Engines for Graphics Processing292-7 Integrated Graphics Controller Unit Block Diagram292.4.2 Integrated Graphics Display Pipes322-8 Processor Display Block Diagram322-3 eDP/PEG Ball Mapping332.4.3 Intel Flexible Display Interface34Platform Environment Control Interface (PECI)34Interface Clocking352.6.1 Internal Clocking Requirements352-4 Processor Reference Clocks35Technologies36Intel® Virtualization Technology363.1.1 Intel® VT-x Objectives363.1.2 Intel® VT-x Features36Intel Graphics Dynamic Frequency37ACPI States Supported384.1.1 System States384.1.2 Processor Core/Package Idle States384-5 System States384-6 Processor Core/Package State Support384.1.3 Integrated Memory Controller States394.1.4 PCIe Link States394.1.5 DMI States394.1.6 Integrated Graphics Controller States394-7 Integrated Memory Controller States394-8 PCIe Link States394-9 DMI States394-10 Integrated Graphics Controller States394.1.7 Interface State Combinations40Processor Core Power Management404-11 G, S and C State Combinations404-12 D, S, and C State Combination404.2.1 Enhanced Intel SpeedStep® Technology414.2.2 Low-Power Idle States414-9 Idle Power Management Breakdown of the Processor Cores424-10 Thread and Core C-State Entry and Exit424.2.3 Requesting Low-Power Idle States434-13 Coordination of Thread Power States at the Core Level434-14 P_LVLx to MWAIT Conversion434.2.4 Core C-states444.2.5 Package C-States454-15 Coordination of Core Power States at the Package Level464-11 Package C-State Entry and Exit47IMC Power Management484.3.1 Disabling Unused System Memory Outputs494.3.2 DRAM Power Management and Initialization49PCIe Power Management504-16 Targeted Memory State Conditions50DMI Power Management51Integrated Graphics Power Management514.6.1 Intel® Display Power Saving Technology 5.0 (Intel ® DPST 5.0)514.6.2 Graphics Render C-State514.6.3 Graphics Performance Modulation Technology514.6.4 Intel® Smart 2D Display Technology (Intel® S2DDT)51Thermal Power Management52Thermal Design Power and Junction Temperature535.1.1 Intel Graphics Dynamic Frequency53Specifications545.1.3 Idle Power Specifications56Specifications565-18 18 W Ultra Low Voltage (ULV) Processor Idle Power565.1.4 Intelligent Power Sharing Control Overview575-19 35 W Standard Voltage (SV) Processor Idle Power575.1.5 Component Power Measurement/Estimation Error58Thermal Management Features585.2.1 Processor Core Thermal Features585-12 Frequency and Voltage Ordering605.2.2 Integrated Graphics and Memory Controller Thermal Features655.2.3 Platform Environment Control Interface (PECI)686-20 Signal Description Buffer Types70System Memory Interface716-21 Memory Channel A716-22 Memory Channel B72Memory Reference and Compensation736-23 Memory Reference and Compensation73Reset and Miscellaneous Signals746-24 Reset and Miscellaneous Signals74PCI Express Graphics Interface Signals756-25 PCI Express Graphics Interface Signals75Embedded DisplayPort (eDP)76Intel Flexible Display Interface Signals766-26 Intel® Flexible Display Interface76DMI77PLL Signals776-27 DMI - Processor to PCH Serial Interface776-28 PLL Signals77TAP Signals786-29 TAP Signals78Error and Thermal Protection796-30 Error and Thermal Protection79Power Sequencing806-31 Power Sequencing80Processor Power Signals816-32 Processor Power Signals81Ground and NCTF83Processor Internal Pull Up/Pull Down836-33 Ground and NCTF836-34 Processor Internal Pull Up/Pull Down83Electrical Specifications85Power and Ground Pins85Decoupling Guidelines857.2.1 Voltage Rail Decoupling85Processor Clocking (BCLK, BCLK#)857.3.1 PLL Power Supply86Voltage Identification (VID)867-35 Voltage Identification Definition86Reserved or Unused Signals907-36 Market Segment Selection Truth Table for MSID[2:0]90Signal Groups917-37 Signal Groups191Test Access Port (TAP) Connection93Absolute Maximum and Minimum Ratings94Storage Conditions Specifications947-38 Processor Absolute Minimum and Maximum Ratings94DC Specifications957-39 Storage Condition Ratings957.10.1 Voltage and Current Specifications967-13 Active VCC and ICC Loadline (PSI# Asserted)977-14 Active VCC and ICC Loadline (PSI# Not Asserted)97Processor Uncore I/O Buffer Supply DC Voltage and Current Specifications987-15 VAXG/IAXG Static and Ripple Voltage Regulation99Specifications99DDR3 Signal Group DC Specifications100Control Sideband and TAP Signal Group DC Specifications101PCI Express DC Specifications102Platform Environmental Control Interface (PECI) DC Specifications1037.11.1 DC Characteristics103eDP DC Specifications1037.11.2 Input Device Hysteresis1047-16 Input Device Hysteresis104PECI DC Electrical Limits104Processor Pin and Signal Information105Processor Pin Assignments1058-17 Socket-G (rPGA988A) Pinmap (Top View, Upper-Left Quadrant)1068-18 Socket-G (rPGA988A) Pinmap (Top View, Upper-Right Quadrant)1078-19 Socket-G (rPGA988A) Pinmap (Top View, Lower-Left Quadrant)1088-20 Socket-G (rPGA988A) Pinmap (Top View, Lower-Right Quadrant)109rPGA988A Processor Pin List by Pin Number110rPGA988A Processor Pin List by Pin Name1248-21 BGA1288 Ballmap (Top View, Upper-Left Quadrant)1388-22 BGA1288 Ballmap (Top View, Upper-Right Quadrant)1398-23 BGA1288 Ballmap (Top View, Lower-Left Quadrant)1408-24 BGA1288 Ballmap (Top View, Lower-Right Quadrant)141BGA1288 Processor Ball List by Ball Name142BGA1288 Processor Ball List by Ball Number160Package Mechanical Information1798-25 rPGA Mechanical Package (Sheet 1 of 2)1798-26 rPGA Mechanical Package (Sheet 2 of 2)1808-27 BGA Mechanical Package (Sheet 2 of 2)181Size: 3.29 MBPages: 181Language: EnglishOpen manual