Intel P4500 CP80617004803AA Data Sheet
Product codes
CP80617004803AA
Power Management
50
Datasheet
4.3.2.3
Dynamic Power Down Operation
Dynamic power-down of memory is employed during normal operation. Based on idle
conditions, a given memory rank may be powered down. The IMC implements
aggressive CKE control to dynamically put the DRAM devices in a power down state.
The processor core controller can be configured to put the devices in active power down
(CKE deassertion with open pages) or precharge power down (CKE deassertion with all
pages closed). Precharge power down provides greater power savings but has a bigger
performance impact, since all pages will first be closed before putting the devices in
power down mode.
conditions, a given memory rank may be powered down. The IMC implements
aggressive CKE control to dynamically put the DRAM devices in a power down state.
The processor core controller can be configured to put the devices in active power down
(CKE deassertion with open pages) or precharge power down (CKE deassertion with all
pages closed). Precharge power down provides greater power savings but has a bigger
performance impact, since all pages will first be closed before putting the devices in
power down mode.
If dynamic power-down is enabled, all ranks are powered up before doing a refresh
cycle and all ranks are powered down at the end of refresh.
cycle and all ranks are powered down at the end of refresh.
4.3.2.4
DRAM I/O Power Management
Unused signals should be disabled to save power and reduce electromagnetic
interference. This includes all signals associated with an unused memory channel.
Clocks can be controlled on a per SO-DIMM basis. Exceptions are made for per SO-
DIMM control signals such as CS#, CKE, and ODT for unpopulated SO-DIMM slots.
interference. This includes all signals associated with an unused memory channel.
Clocks can be controlled on a per SO-DIMM basis. Exceptions are made for per SO-
DIMM control signals such as CS#, CKE, and ODT for unpopulated SO-DIMM slots.
The I/O buffer for an unused signal should be tri-stated (output driver disabled), the
input receiver (differential sense-amp) should be disabled, and any DLL circuitry
related ONLY to unused signals should be disabled. The input path must be gated to
prevent spurious results due to noise on the unused signals (typically handled
automatically when input receiver is disabled).
input receiver (differential sense-amp) should be disabled, and any DLL circuitry
related ONLY to unused signals should be disabled. The input path must be gated to
prevent spurious results due to noise on the unused signals (typically handled
automatically when input receiver is disabled).
4.4
PCIe Power Management
Active power management support using L0s, and L1 states.
All inputs and outputs disabled in L2/L3 Ready state.
Table 4-16.Targeted Memory State Conditions
Mode
Memory State with Internal Graphics
Memory State with External Graphics
C0, C1, C1E
Dynamic memory rank power down based on
idle conditions.
idle conditions.
Dynamic memory rank power down based on
idle conditions.
idle conditions.
C3, C6
If the internal graphics engine is idle and there
are no pending display requests when in single
display mode, then enter self-refresh.
Otherwise use dynamic memory rank power
down based on idle conditions.
are no pending display requests when in single
display mode, then enter self-refresh.
Otherwise use dynamic memory rank power
down based on idle conditions.
If there are no memory requests, then enter
self-refresh. Otherwise use dynamic memory
rank power down based on idle conditions.
self-refresh. Otherwise use dynamic memory
rank power down based on idle conditions.
S3
Self-Refresh Mode.
Self-Refresh Mode.
S4
Memory power down (contents lost).
Memory power down (contents lost)