Intel P4500 CP80617004803AA Data Sheet
Product codes
CP80617004803AA
Datasheet
61
Thermal Management
If a processor load-based Enhanced Intel SpeedStep Technology/P-state transition
(through MSR write) is initiated while the Adaptive Thermal Monitor is active, there are
two possible outcomes:
(through MSR write) is initiated while the Adaptive Thermal Monitor is active, there are
two possible outcomes:
If the P-state target frequency is higher than the processor core optimized target
frequency, the p-state transition will be deferred until the thermal event has been
completed.
frequency, the p-state transition will be deferred until the thermal event has been
completed.
If the P-state target frequency is lower than the processor core optimized target
frequency, the processor will transition to the P-state operating point.
frequency, the processor will transition to the P-state operating point.
5.2.1.1.2
Clock Modulation
If the frequency/voltage changes are unable to end an Adaptive Thermal Monitor
event, the Adaptive Thermal Monitor will utilize clock modulation. Clock modulation is
done by alternately turning the clocks off and on at a duty cycle (ratio between clock
on time and total time) specific to the processor. The duty cycle is factory configured
to 37.5% on and 62.5% off and cannot be modified. The period of the duty cycle is
configured to 32 microseconds when the TCC is active. Cycle times are independent of
processor frequency. A small amount of hysteresis has been included to prevent
excessive clock modulation when the processor temperature is near its maximum
operating temperature. Once the temperature has dropped below the maximum
operating temperature, and the hysteresis timer has expired, the TCC goes inactive and
clock modulation ceases. Clock modulation is automatically engaged as part of the TCC
activation when the frequency/VID targets are at their minimum settings. Processor
performance will be decreased by the same amount as the duty cycle when clock
modulation is active. Snooping and interrupt processing are performed in the normal
manner while the TCC is active.
event, the Adaptive Thermal Monitor will utilize clock modulation. Clock modulation is
done by alternately turning the clocks off and on at a duty cycle (ratio between clock
on time and total time) specific to the processor. The duty cycle is factory configured
to 37.5% on and 62.5% off and cannot be modified. The period of the duty cycle is
configured to 32 microseconds when the TCC is active. Cycle times are independent of
processor frequency. A small amount of hysteresis has been included to prevent
excessive clock modulation when the processor temperature is near its maximum
operating temperature. Once the temperature has dropped below the maximum
operating temperature, and the hysteresis timer has expired, the TCC goes inactive and
clock modulation ceases. Clock modulation is automatically engaged as part of the TCC
activation when the frequency/VID targets are at their minimum settings. Processor
performance will be decreased by the same amount as the duty cycle when clock
modulation is active. Snooping and interrupt processing are performed in the normal
manner while the TCC is active.
5.2.1.2
Digital Thermal Sensor
Each processor execution core has an on-die Digital Thermal Sensor (DTS) which
detects the cores instantaneous temperature. The DTS is the preferred method of
monitoring processor die temperature because
detects the cores instantaneous temperature. The DTS is the preferred method of
monitoring processor die temperature because
It is located near the hottest portions of the die.
It can accurately track the die temperature and ensure that the Adaptive Thermal
Monitor is not excessively activated.
Monitor is not excessively activated.
Temperature values from the DTS can be retrieved through
A software interface via processor Model Specific Register (MSR).
A processor hardware interface as described in
Platform Environment Control
Interface (PECI) on page 68
.
Note:
When temperature is retrieved by processor MSR, it is the instantaneous temperature
of the given core. When temperature is retrieved via PECI, it is the average
temperature of each execution cores DTS over a programmable window (default
window of 256 ms.) Intel recommends using the PECI output reading for fan speed or
other platform thermal control.
of the given core. When temperature is retrieved via PECI, it is the average
temperature of each execution cores DTS over a programmable window (default
window of 256 ms.) Intel recommends using the PECI output reading for fan speed or
other platform thermal control.