Intel P4500 CP80617004803AA Data Sheet
Product codes
CP80617004803AA
Electrical Specifications
86
Datasheet
7.3.1
PLL Power Supply
An on-die PLL filter solution is implemented on the processor. Refer to
Table 7-35
for
DC specifications
7.4
Voltage Identification (VID)
The processor uses seven voltage identification pins, VID[6:0], to support automatic
selection of the processor power supply voltages. VID pins for the processor are CMOS
outputs driven by the processor VID circuitry. A dedicated graphics voltage regulator is
required to deliver voltage to the integrated graphics controller. Like the processor
core, the integrated graphics controller will use seven voltage identification pins,
GFX_VID[6:0], to set the nominal operating voltage GFX_VID pins for the graphics core
are CMOS outputs driven by the graphics core VID circuitry.
selection of the processor power supply voltages. VID pins for the processor are CMOS
outputs driven by the processor VID circuitry. A dedicated graphics voltage regulator is
required to deliver voltage to the integrated graphics controller. Like the processor
core, the integrated graphics controller will use seven voltage identification pins,
GFX_VID[6:0], to set the nominal operating voltage GFX_VID pins for the graphics core
are CMOS outputs driven by the graphics core VID circuitry.
Table 7-35
specifies the
voltage level for VID[6:0] and GFX_VID[6:0]; 0 refers to a low-voltage level
VID signals are CMOS push/pull drivers. Refer to
Table 7-44
for the DC specifications
for these signals. The VID codes will change due to temperature, frequency, and/or
power mode load changes in order to minimize the power of the part. A voltage range
is provided in
power mode load changes in order to minimize the power of the part. A voltage range
is provided in
Table 7-35
. The specifications are set so that one voltage regulator can
operate with all supported frequencies.
Individual processor VID values may be set during manufacturing so that two devices
at the same core frequency may have different default VID settings. This is shown in
the VID range values in
at the same core frequency may have different default VID settings. This is shown in
the VID range values in
Table 7-35
. The processor
provides the ability to operate while
transitioning to an adjacent VID and its associated processor core voltage (V
CC
). This
will represent a DC shift in the loadline.
Note:
A low-to-high or high-to-low voltage state change will result in as many VID transitions
as necessary to reach the target core voltage. Transitions above the maximum or below
the minimum specified VID are not permitted. One VID transition occurs in 2.5 µs.
as necessary to reach the target core voltage. Transitions above the maximum or below
the minimum specified VID are not permitted. One VID transition occurs in 2.5 µs.
The VR utilized must be capable of regulating its output to the value defined by the new
VID values issued. DC specifications for dynamic VID transitions are included in
VID values issued. DC specifications for dynamic VID transitions are included in
Table 7-35
.
Several of the VID signals (VID[5:3]/CSC[2:0] and VID[2:0]/MSID[2:0]) serve a dual
purpose and are sampled during reset. Refer to the signal description table in
purpose and are sampled during reset. Refer to the signal description table in
Chapter 6
for more information.
Table 7-35.Voltage Identification Definition (Sheet 1 of 4)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
V
CC
(V)
0
0
0
0
0
0
0
1.5000
0
0
0
0
0
0
1
1.4875
0
0
0
0
0
1
0
1.4750
0
0
0
0
0
1
1
1.4625
0
0
0
0
1
0
0
1.4500
0
0
0
0
1
0
1
1.4375
0
0
0
0
1
1
0
1.4250