Intel i7-2600 CM8062300834302S User Manual

Product codes
CM8062300834302S
Page of 296
Processor Configuration Registers
168
Datasheet, Volume 2
2.10.31 MA—Message Address Register
2.10.32 MD—Message Data Register
2.10.33 PEG_CAPL—PCI Express-G Capability List Register
This register enumerates the PCI Express capability structure.
B/D/F/Type:
0/6/0/PCI
Address Offset:
94–97h
Reset Value:
0000_0000h
Access:
RW, RO
Size:
32 bits
Bit
Attr
Reset 
Value
RST/
PWR
Description
31:2
RW
0000_000
0h
Uncore
Message Address (MA)
This field is used by system software to assign an MSI address to 
the device. The device handles an MSI by writing the padded 
contents of the MD register to this address.
1:0
RO
00b
Uncore
Force DWord Align (FDWA)
Hardwired to 00 so that addresses assigned by system software 
are always aligned on a dword address boundary.
B/D/F/Type:
0/6/0/PCI
Address Offset:
98–99h
Reset Value:
0000h
Access:
RW
Size:
16 bits
Bit
Attr
Reset 
Value
RST/
PWR
Description
15:0
RW
0000h
Uncore
Message Data (MD)
Base message data pattern assigned by system software and used 
to handle an MSI from the device. 
When the device must generate an interrupt request, it writes a 
32-bit value to the memory address specified in the MA register. 
The upper 16 bits are always set to 0. The lower 16 bits are 
supplied by this register.
B/D/F/Type:
0/6/0/PCI
Address Offset:
A0–A1h
Reset Value:
0010h
Access:
RO
Size:
16 bits
Bit
Attr
Reset 
Value
RST/
PWR
Description
15:8
RO
00h
Uncore
Pointer to Next Capability (PNC)
This value terminates the capabilities list. The Virtual Channel 
capability and any other PCI Express specific capabilities that are 
reported using this mechanism are in a separate capabilities list 
located entirely within PCI Express Extended Configuration Space.
7:0
RO
10h
Uncore
Capability ID (CID)
This field identifies this linked list item (capability structure) as 
being for PCI Express registers.