Intel i7-2600 CM8062300834302S User Manual
Product codes
CM8062300834302S
Processor Configuration Registers
170
Datasheet, Volume 2
2.10.36 DCTL—Device Control Register
This register provides control for PCI Express device specific capabilities.
The error reporting enable bits are in reference to errors detected by this device, not
error messages received across the link. The reporting of error messages (ERR_CORR,
ERR_NONFATAL, ERR_FATAL) received by Root Port is controlled exclusively by Root
Port Command Register.
error messages received across the link. The reporting of error messages (ERR_CORR,
ERR_NONFATAL, ERR_FATAL) received by Root Port is controlled exclusively by Root
Port Command Register.
B/D/F/Type:
0/6/0/PCI
Address Offset:
A8–A9h
Reset Value:
0000h
Access:
RO, RW
Size:
16 bits
BIOS Optimal Default
0h
Bit
Attr
Reset
Value
RST/
PWR
Description
15
RO
0h
Reserved
14:12
RO
000b
Uncore
Reserved for Max Read Request Size (MRRS)
11
RO
0b
Uncore
Reserved for Enable No Snoop (NSE)
10:8
RO
0h
Reserved
7:5
RW
000b
Uncore
Max Payload Size (MPS)
000 = 128B maximum payload for Transaction Layer Packets (TLP)
All other encodings are reserved.
As a receiver, the device must handle TLPs as larger as the value set
000 = 128B maximum payload for Transaction Layer Packets (TLP)
All other encodings are reserved.
As a receiver, the device must handle TLPs as larger as the value set
in this field. As a transmitter, the device must not generate TLPs
exceeding the value set in this field.
4
RO
0b
Uncore
Reserved for Enable Relaxed Ordering (ROE)
3
RW
0b
Uncore
Unsupported Request Reporting Enable (URRE)
When set, this bit allows signaling ERR_NONFATAL, ERR_FATAL, or
When set, this bit allows signaling ERR_NONFATAL, ERR_FATAL, or
ERR_CORR to the Root Control register when detecting an
unmasked Unsupported Request (UR). An ERR_CORR is signaled
when an unmasked Advisory Non-Fatal UR is received. An
ERR_FATAL or ERR_NONFATAL is sent to the Root Control register
when an uncorrectable non-Advisory UR is received with the severity
bit set in the Uncorrectable Error Severity register.
2
RW
0b
Uncore
Fatal Error Reporting Enable (FERE)
When set, this bit enables signaling of ERR_FATAL to the Root
When set, this bit enables signaling of ERR_FATAL to the Root
Control register due to internally detected errors or error messages
received across the link. Other bits also control the full scope of
related error reporting.
1
RW
0b
Uncore
Non-Fatal Error Reporting Enable (NERE)
When set, this bit enables signaling of ERR_NONFATAL to the Rool
When set, this bit enables signaling of ERR_NONFATAL to the Rool
Control register due to internally detected errors or error messages
received across the link. Other bits also control the full scope of
related error reporting.
0
RW
0b
Uncore
Correctable Error Reporting Enable (CERE)
When set, this bit enables signaling of ERR_CORR to the Root
When set, this bit enables signaling of ERR_CORR to the Root
Control register due to internally detected errors or error messages
received across the link. Other bits also control the full scope of
related error reporting.