Intel i7-2600 CM8062300834302S User Manual

Datasheet, Volume 2

291

This register specifies the Invalidation Event interrupt message data. This register is 
treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not 
supported in the Extended Capability register.

This register specifies the Invalidation Event Interrupt message address. This register 
is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not 
supported in the Extended Capability register.

31:16

RW-L

0000h

Uncore

Extended Interrupt Message Data (EIMD)
This field is valid only for implementations supporting 32-bit 

interrupt data fields.
Hardware implementations supporting only 16-bit interrupt data 

treat this field as Rsvd. 

15:0

RW-L

0000h

Uncore

Interrupt Message data (IMD)
Data value in the interrupt request. 

31:2

RW-L

00000000h

Uncore

Message address (MA)
When fault events are enabled, the contents of this register specify 

the DWORD-aligned address (bits 31:2) for the interrupt request. 

1:0

RO

0h