Intel i7-2600 CM8062300834302S User Manual

292

Datasheet, Volume 2

This register specifies the Invalidation Event interrupt message upper address.

This register provides the base address of Interrupt remapping table. This register is 
treated as RsvdZ by implementations reporting Interrupt Remapping (IR) as not 
supported in the Extended Capability register.

31:0

RW-L

0000_000

0h

Uncore

Message Upper Address (MUA)
Hardware implementations supporting Queued Invalidations and 

Extended Interrupt Mode are required to implement this register.
Hardware implementations not supporting Queued Invalidations or 

Extended Interrupt Mode may treat this field as RsvdZ.

63:39

RO

0h

38:12

RW-L

0000000h

Uncore

Interrupt Remapping Table Address (IRTA)
This field points to the base of 4KB aligned interrupt remapping 

table.
Hardware ignores and does not implement bits 63:HAW, where 

HAW is the host address width.
Reads of this field returns value that was last programmed to it. 

11

RW-L

0b

Uncore

Extended Interrupt Mode Enable (EIME)
This field is used by hardware on Intel 64 platforms as follows:
0 = xAPIC mode is active. Hardware interprets only low 8-bits of 

Destination-ID field in the IRTEs. The high 24-bits of the 

Destination-ID field are treated as reserved.

1 = x2APIC mode is active. Hardware interprets all 32-bits of 

Destination-ID field in the IRTEs.

This field is implemented as RsvdZ on implementations reporting 

Extended Interrupt Mode (EIM) field as Clear in Extended 

Capability register.

10:4

RO

0h

3:0

RW-L

0h

Uncore

Size (S)
This field specifies the size of the interrupt remapping table. The 

number of entries in the interrupt remapping table is 2^(X+1), 

where X is the value programmed in this field.