Intel i5-2510E FF8062700853304 User Manual
Product codes
FF8062700853304
Datasheet
23
Interfaces
2.1.4
Rules for Populating Memory Slots
In all modes, the frequency of system memory is the lowest frequency of all memory
modules placed in the system, as determined through the SPD registers on the
memory modules. The system memory controller supports only one SO-DIMM
connector per channel. For dual-channel modes both channels must have an SO-DIMM
connector populated. For single-channel mode, only a single-channel can have an
SO-DIMM connector populated.
2.1.5
Technology Enhancements of Intel® Fast Memory Access
(Intel® FMA)
The following sections describe the Just-in-Time Scheduling, Command Overlap, and
Out-of-Order Scheduling Intel FMA technology enhancements.
2.1.5.1
Just-in-Time Command Scheduling
The memory controller has an advanced command scheduler where all pending
requests are examined simultaneously to determine the most efficient request to be
issued next. The most efficient request is picked from all pending requests and issued
to system memory Just-in-Time to make optimal use of Command Overlapping. Thus,
instead of having all memory access requests go individually through an arbitration
mechanism forcing requests to be executed one at a time, they can be started without
interfering with the current request allowing for concurrent issuing of requests. This
allows for optimized bandwidth and reduced latency while maintaining appropriate
command spacing to meet system memory protocol.
Figure 3.
Dual-Channel Symmetric (Interleaved) and Dual-Channel Asymmetric Modes
CH. B
CH. A
CH. B
CH. A
CH. B
CH. A
CL
0
Top of
Memory
CL
0
CH. B
CH. A
CH.A-top
DRB
DRB
Dual Channel Interleaved
(memory sizes must match)
Dual Channel Asymmetric
(memory sizes can differ)
Top of
Memory