Intel i5-2520M FF8062700840017 User Manual

26

Datasheet

The transmission side of the Data Link Layer accepts TLPs assembled by the 

Transaction Layer, calculates and applies data protection code and TLP sequence 

number, and submits them to Physical Layer for transmission across the Link. The 

receiving Data Link Layer is responsible for checking the integrity of received TLPs and 

for submitting them to the Transaction Layer for further processing. On detection of TLP 

error(s), this layer is responsible for requesting retransmission of TLPs until information 

is correctly received, or the Link is determined to have failed. The Data Link Layer also 

generates and consumes packets which are used for Link management functions.

The Physical Layer includes all circuitry for interface operation, including driver and 

input buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s), and impedance 

matching circuitry. It also includes logical functions related to interface initialization and 

maintenance. The Physical Layer exchanges data with the Data Link Layer in an 

implementation-specific format, and is responsible for converting this to an appropriate 

serialized format and transmitting it across the PCI Express Link at a frequency and 

width compatible with the remote device.

The PCI Express (external graphics) link is mapped through a PCI-to-PCI bridge 

structure.

PCI Express extends the configuration space to 4096 bytes per-device/function, as 

compared to 256 bytes allowed by the Conventional PCI Specification. PCI Express 

configuration space is divided into a PCI-compatible region (which consists of the first 

256 bytes of a logical device's configuration space) and an extended PCI Express region 

(which consists of the remaining configuration space). The PCI-compatible region can 

be accessed using either the mechanisms defined in the PCI specification or using the 

enhanced PCI Express configuration access mechanism described in the PCI Express 

Enhanced Configuration Mechanism section.

PCI-PCI 

Bridge 

representing 

root PCI 

Express port 

(Device 1)

PCI 

Compatible 

Host Bridge 

Device

(Device 0)