Intel i5-2520M FF8062700840017 User Manual

Datasheet

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The PCI Express Host Bridge is required to translate the memory-mapped PCI Express 

configuration space accesses from the host processor to PCI Express configuration 

cycles. To maintain compatibility with PCI configuration addressing mechanisms, it is 

recommended that system software access the enhanced configuration space using 

32-bit operations (32-bit aligned) only. See the PCI Express Base Specification for 

details of both the PCI-compatible and PCI Express Enhanced configuration 

mechanisms and transaction rules.

The external graphics attach (PEG) on the processor is a single, 16-lane (x16) port. The 

PEG port is being designed to be compliant with the PCI Express Base Specification, 

DMI connects the processor and the PCH chip-to-chip. DMI2 is supported. The DMI is 

similar to a four-lane PCI Express supporting up to 1 GB/s of bandwidth in each 

direction. 

Only DMI x4 configuration is supported.

DMI can only generate SERR in response to errors, never SCI, SMI, MSI, PCI INT, or 

GPE. Any DMI related SERR activity is associated with Device 0.

The processor is compatible with the PCH and is not compatible with any previous 

(G)MCH or ICH products.

The DMI link going down is a fatal, unrecoverable error. If the DMI data link goes to 

data link down, after the link was up, then the DMI link hangs the system by not 

allowing the link to retrain to prevent data corruption. This is controlled by the PCH.

Downstream transactions that had been successfully transmitted across the link prior 

to the link going down may be processed as normal. No completions from downstream, 

non-posted transactions are returned upstream over the DMI link after a link down 

event.

This section details the 2D, 3D and video pipeline and their respective capabilities.

The integrated graphics is powered by a refresh of the fifth generation graphics core 

and supports twelve, fully-programmable execution cores. Full-precision, floating-point 

operations are supported to enhance the visual experience of compute-intensive 

applications.The integrated graphics controller contains several types of components; 

the graphics engines, planes, pipes, port and the Intel FDI. The integrated graphics has 

a 3D/2D Instruction Processing unit to control the 3D and 2D engines respectively. The 

integrated graphics controller’s 3D and 2D engines are fed with data through the IMC.