Intel III 600 MHz 80526PY600256 User Manual
Product codes
80526PY600256
Datasheet
23
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
The groups and the signals contained within each group are shown in
Table 3
and
Table 4
. Refer to
Section 7.0
for a description of these signals.
NOTES:
1. See
Section 7.0
for information on the these signals.
2. The BR0# pin is the only BREQ# signal that is bidirectional. See
Section 7.0
for more information. The
internal BREQ# signals are mapped onto the BR[1:0]# pins after the agent ID is determined.
3. These signals are specified for Vcc
CMOS
(1.5 V for the Pentium III processor) operation.
4. These signals are 2.5 V tolerant.
5. V
5. V
CC
CORE
is the power supply for the processor core and is described in
Section 2.6
.
VID[3:0] is described in
Section 2.6
.
V
TT
is used to terminate the system bus and generate V
REF
on the motherboard.
V
SS
is system ground.
V
CC
1.5
,
V
CC
2.5
,
Vcc
CMOS
are described in
Section 2.3
.
BSEL[1:0] is described in
Section 2.8.2
and
Section 7.0
.
All other signals are described in
Section 7.0
.
6. RESET# must always be terminated to V
TT
on the motherboard, on-die termination is not provided for this
signal.
7. This signal is not supported by all processors. Refer to the Pentium
®
III Processor Specification Update for a
complete listing of processors that support this pin.
8. This signal is used to control the value of the processor on-die termination resistance. Refer to the platform
design guide for the recommended pull-down resistor value.
Table 3.
System Bus Signal Groups
1
Group Name
Signals
AGTL+ Input
BPRI#, BR1#
7
, DEFER#, RESET#
6
,RESET2#, RS[2:0]#, RSP#, TRDY#
AGTL+ Output
PRDY#
AGTL+ I/O
A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#,
BR0#
BR0#
2
, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#, LOCK#, REQ[4:0]#, RP#
CMOS Input
3
A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SLP#, SMI#,
STPCLK#
STPCLK#
CMOS Input
4
PWRGOOD
CMOS Output
3
FERR#, IERR#, THERMTRIP#
System Bus
Clock
Clock
4
BCLK
APIC Clock
4
PICCLK
APIC I/O
3
PICD[1:0]
Power/Other
5
BSEL[1:0], CLKREF, CPUPRES#, EDGCTRL, PLL[2:1], RESET2#, SLEWCTRL,
THERMDN, THERMDP, RTTCTRL
THERMDN, THERMDP, RTTCTRL
8
, V
COREDET
, VID[3:0], V
CC1.5
,
V
CC2.5
,
V
CCCMOS
,
V
CC
CORE
, V
REF
, V
SS
, V
TT
, Reserved
Table 4.
System Bus Signal Groups (AGTL)
1
(Sheet 1 of 2)
Group Name
Signals
AGTL Input
9
BPRI#, BR1#
7
, DEFER#, RESET#
6
, RSP#, TRDY#, RS[2:0]#
AGTL Output
9
PRDY#
AGTL I/O
9
A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#,
BR0#
BR0#
2
, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#, LOCK#, REQ[4:0]#, RP#,
CMOS Input
3
A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SLP#, SMI#,
STPCLK#
STPCLK#
CMOS Input
(1.8 V)
(1.8 V)
PWRGOOD
CMOS Output
FERR#
3
, IERR#
3
, THERMTRIP#
3
, VID[3:0]
13
, BSEL[1:0]
13