Intel III 600 MHz 80526PY600256 User Manual
Product codes
80526PY600256
24
Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
NOTES:
1. See
Section 7.0
for information on the these signals.
2. The BR0# pin is the only BREQ# signal that is bidirectional. See
Section 7.0
for more information. The
internal BREQ# signals are mapped onto the BR[1:0]# pins after the agent ID is determined.
3. These signals are specified for Vcc
CMOS
(1.5 V for the Pentium III processor) operation.
4. These signals are 2.5 V tolerant.
5. V
5. V
CC
CORE
is the power supply for the processor core and is described in
Section 2.6
.
VID[3:0] is described in
Section 2.6
.
V
TT
is used to terminate the system bus and generate V
REF
on the motherboard.
V
SS
is system ground.
V
CC
1.5
,
V
CC
2.5
,
Vcc
CMOS
are described in
Section 2.3
.
BSEL[1:0] is described in
Section 2.8.2
and
Section 7.0
.
All other signals are described in
Section 7.0
.
6. RESET# must always be terminated to V
TT
on the motherboard, on-die termination is not provided for this
signal.
7. This signal is not supported by all processors. Refer to the Pentium
®
III Processor Specification Update for a
complete listing of processors that support this pin.
8. This signal is used to control the value of the processor on-die termination resistance. Refer to the platform
design guide for the recommended pull-down resistor value.
9. These signals are also classified as AGTL. Refer to the Pentium
®
III Processor Specification Update for a
complete listing of processors that support the AGTL and AGTL+ specifications.
10.For differential clock systems, the CLKREF pin becomes BCLK#.
11. For the Coppermine-T differential clock, this signal has been redefined to 2.0 V tolerant.
12. 1.25 V signal for Differential clock application and 2.5 V for Single-ended clock application.
13. This signal is 3.3 V.
13. This signal is 3.3 V.
2.8.1
Asynchronous vs. Synchronous for System Bus Signals
All AGTL+ signals are synchronous to BCLK. All of the CMOS, Clock, APIC, and TAP signals
can be applied asynchronously to BCLK. All APIC signals are synchronous to PICCLK.
can be applied asynchronously to BCLK. All APIC signals are synchronous to PICCLK.
System Bus
Clock
Clock
10, 12
(1.25 V/2.5 V)
BCLK, BCLK0#
APIC Clock
(2.0 V)
(2.0 V)
PICCLK
11
APIC I/O
3
PICD[1:0]
Power/Other
5
BSEL[1:0], CLKREF
10
, CPUPRES#, EDGCTRL, PLL[2:1], RESET2#, SLEWCTRL,
THERMDN, THERMDP, RTTCTRL
8
, V
COREDET
, VID[3:0], V
CC1.5
,
V
CC2.5
,
V
CCCMOS
,
V
CC
CORE
, V
REF
, V
SS
, V
TT
, Reserved
Table 4.
System Bus Signal Groups (AGTL)
1
(Sheet 2 of 2)
Group Name
Signals