Intel III 600 MHz 80526PY600256 User Manual
Product codes
80526PY600256
38
Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
3. Not 100% tested. Specified by design characterization as a clock driver requirement.
4. The internal core clock frequency is derived from the processor system bus clock. The system bus clock to
4. The internal core clock frequency is derived from the processor system bus clock. The system bus clock to
core clock ratio is determined during initialization. Individual processors will only operate at their specified
system bus frequency, either 100 MHz or 133 MHz, not both.
system bus frequency, either 100 MHz or 133 MHz, not both.
5. The BCLK period allows a +0.5 ns tolerance for clock driver variation. See the appropriate clock synthesizer/
driver specification for details.
6. Due to the difficulty of accurately measuring clock jitter in a system, it is recommended that a clock driver be
used that is designed to meet the period stability specification into a test load of 10 to 20 pF. This should be
measured on the rising edges of adjacent BCLKs crossing 1.25 V at the processor pin. The jitter present
must be accounted for as a component of BCLK timing skew between devices.
measured on the rising edges of adjacent BCLKs crossing 1.25 V at the processor pin. The jitter present
must be accounted for as a component of BCLK timing skew between devices.
7. The clock driver’s closed loop jitter bandwidth must be set low to allow any PLL-based device to track the
jitter created by the clock driver. The –20 dB attenuation point, as measured into a 10 to 20 pF load, should
be less than
be less than
500 kHz. This specification may be ensured by design characterization and/or measured with a
spectrum analyzer. See the appropriate clock synthesizer/driver specification for details
8. BCLK Rise time is measure between 0.5 V–2.0 V. BCLK fall time is measured between 2.0 V–0.5 V.
9. BCLK high time is measured as the period of time above 2.0 V. BCLK low time is measured as the period of
9. BCLK high time is measured as the period of time above 2.0 V. BCLK low time is measured as the period of
time below 0.5 V.
10.This specification applies to Pentium III processors operating at a system bus frequency of 100 MHz.
11. This specification applies to Pentium III processors operating at a system bus frequency of 133 MHz
NOTES:
1. Measurement taken from differential waveform, defined as BCLK - BCLK#.
2. Period is defined from one rising 0 V-crossing to the next.
3. Measurement taken from differential waveform, voltage range from -0.35 V to +0.35 V.
4. Measurement taken from common mode waveform, measure rise/fall time from 0.41 V to 0.86 V. Rise/fall
2. Period is defined from one rising 0 V-crossing to the next.
3. Measurement taken from differential waveform, voltage range from -0.35 V to +0.35 V.
4. Measurement taken from common mode waveform, measure rise/fall time from 0.41 V to 0.86 V. Rise/fall
time matching is defined as “the instantaneous difference between maximum BCLK rise (fall) and minimum
BCLK# fall (rise) time, or minimum BCLK rise (fall) and maximum BCLK# fall (rise) time. “This parameter is
designed to guard waveform symmetry.
BCLK# fall (rise) time, or minimum BCLK rise (fall) and maximum BCLK# fall (rise) time. “This parameter is
designed to guard waveform symmetry.
5. Period difference measured around 0 V-crossings; measurement taken from differential waveform.
6. The rising and falling edge ringback voltage specified is the minimum (rising) or them maximum (falling)
6. The rising and falling edge ringback voltage specified is the minimum (rising) or them maximum (falling)
voltage, the differential waveform can go after passing Vih_diff (rising) or Vil_diff (falling)
7. Measured in absolute voltage, i.e. single-ended measurement. Includes every cross point for both rise and
fall of BCLK.
8. Input high or input low voltage range measured in absolute voltage, i.e. single-ended measurement.
9. The internal Core clock frequency is derived from the processor system bus clock. The system bus clock to
9. The internal Core clock frequency is derived from the processor system bus clock. The system bus clock to
core clock ratio is determined during initialization. Individual processors will only operate at their specified
system bus frequency 133 MHz. Table 16 shows supported ratios for each processor
system bus frequency 133 MHz. Table 16 shows supported ratios for each processor
10.Due to the difficulty of accurately measuring clock jitter in a system, it is recommended that a clock driver be
used that is designed to meet the period stability specification into a test load of 10 pF to 20 pF. The jitter
must be accounted for as a component of BCLK timing skew between devices.
must be accounted for as a component of BCLK timing skew between devices.
11. AC parameters are measured at the processor pins.
12.BCLK/BCLK# must rise/fall monotonically between Vil and Vih.
Table 15. System Bus Timing Specifications (Differential Clock)
1, 11, 12
Parameter
133 MHz
100 MHz
Units
Notes
Min
Max
Min
Max
Clock Period—Average
7.5
7.7
10.0
10.2
ns
2, 9, 10
Instantaneous Minimum Clock Period
7.30
9.8
ns
2, 9, 10
CLK Differential Rise Time
175
550
175
467
ps
1, 3
CLK Differential Fall Time
175
550
175
467
ps
1, 3
Waveform Symmetry
325
325
ps
4
Differential Cycle to Cycle Jitter
200
200
ps
1, 5
Differential Duty Cycle
45%
55%
45%
55%
1
Rising Edge Ring Back
0.35
0.35
V
1, 6
Falling Edge Ring Back
–0.35
–0.35
V
1, 6
Cross Point at 1V
0.51
0.76
0.51
0.76
V
7
Input High Voltage
0.92
1.45
0.92
1.45
V
8
Input Low Voltage
–0.2
0.35
–0.2
0.35
V
8