Intel III 600 MHz 80526PY600256 User Manual
Product codes
80526PY600256
40
Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies
2. These specifications are tested during manufacturing.
3. These signals may be driven asynchronously.
4. All CMOS outputs shall be asserted for at least 2 BCLKs.
5. When driven inactive or after V
2. These specifications are tested during manufacturing.
3. These signals may be driven asynchronously.
4. All CMOS outputs shall be asserted for at least 2 BCLKs.
5. When driven inactive or after V
CCCORE
, V
TT
, V
CCCMOS
, and BCLK become stable.
NOTE: 1. Unless otherwise noted, all specifications in this table apply to all Pentium III processor frequencies.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the APIC I/O signals are referenced to the PICCLK rising edge at 1.25 V at the processor
2. These specifications are tested during manufacturing.
3. All AC timings for the APIC I/O signals are referenced to the PICCLK rising edge at 1.25 V at the processor
pins. All APIC I/O signal timings are referenced at 0.75 V at the processor pins.
4. Referenced to PICCLK rising edge.
5. For open drain signals, valid delay is synonymous with float delay.
6. Valid delay timings for these signals are specified into 150
5. For open drain signals, valid delay is synonymous with float delay.
6. Valid delay timings for these signals are specified into 150
Ω
load pulled up to 1.5 V.
NOTES:
Table 17. System Bus AC Specifications (CMOS Signal Group)
1, 2, 3, 4
T# Parameter
Min
Max
Unit
Figure
Notes
T14: CMOS Input Pulse Width, except
PWRGOOD
2
BCLKs
11
Active and
Inactive states
Inactive states
T15: PWRGOOD Inactive Pulse Width
10
BCLKs
11
,
14
5
Table 18. System Bus AC Specifications (Reset Conditions)
1
T# Parameter
Min
Max
Unit
Figure
Notes
T16: Reset Configuration Signals
(A[14:5]#, BR0#, INIT#) Setup Time
4
BCLKs
13
Before deassertion
of RESET#
of RESET#
T17: Reset Configuration Signals
(A[14:5]#, BR0#, INIT#) Hold Time
2
20
BCLKs
13
After clock that
deasserts RESET#
deasserts RESET#
Table 19. System Bus AC Specifications (APIC Clock and APIC I/O)
1, 2, 3
T# Parameter
Min
Max
Unit
Figure
Notes
T21: PICCLK Frequency
2.0
33.3
MHz
T22: PICCLK Period
30.0
500.0
ns
9
T23: PICCLK High Time
10.5
ns
9
@ > 1.7V
T24: PICCLK Low Time
10.5
ns
9
@ < 0.7V
T25: PICCLK Rise Time
0.25
3.0
ns
9
(0.7V - 1.7V)
T26: PICCLK Fall Time
0.25
3.0
ns
9
(1.7V - 0.7V)
T27: PICD[1:0] Setup Time
5.0
ns
12
4
T28: PICD[1:0] Hold Time
2.5
ns
12
4
T29a: PICD[1:0] Valid Delay (Rising Edge)
1.5
8.7
ns
10
,
11
4, 5, 6
T29b: PICD[1:0] Valid Delay (Falling Edge)
1.5
12.0
ns
10
,
11
4, 5, 6
Table 20. Platform Power-On Timings
2
T# Parameter
Min
Max
Unit
Figure
Notes
T45: Valid Time Before VTT_PWRGD
1.0
mS
14
1
T46: Valid Time Before PWRGOOD
2.0
mS
14
1
T47: RESET# Inactive to Valid Outputs
1
BCLK
14
1
T48: RESET# Inactive to Drive Signals
4
BCLK
14
1