Intel III Xeon 800 MHz 80526KZ800256 User Manual

 

9 

 
The Pentium® III Xeon™ processor signals use a variation of the Pentium® Pro processor GTL+ signaling technology. 
The Pentium® III Xeon™ processor differs from the Pentium® II processor and Pentium® Pro processor in its output 
buffer implementation. The buffers that drive most of the system bus signals on the Pentium® III Xeon™ processor are 
actively driven to VTT for one clock cycle after the low to high transition to improve rise-times and reduce noise. These 
signals should still be considered open-drain and require termination to a supply that provides the high signal level. 
Because this specification is different from the standard GTL+ specification, it is referred to as Assisted Gunning 
Transistor Logic (AGTL+) in this document. AGTL+ logic and GTL+ logic are compatible with each other and may both be 
used on the same system bus. For more information on the GTL+ specification, see the Pentium II Processor Developer’s 
Manual  (Order Number 243502).  
 
AGTL+ inputs use differential receivers that require a reference signal (VREF). The receivers use VREF to determine if a 
signal is a logical 0 or a logical 1. The Pentium® III Xeon™ processor at 700 MHz and 900 MHz generates its own version 
of VREF. VREF must be generated on the baseboard for other devices on the AGTL+ system bus. Termination is used to 
pull the bus up to the high voltage level and to control signal integrity on the transmission line. The processor contains 
termination resistors, but additional termination on the baseboard may be necessary to maintain proper signal quality and 
timing for the processor and any additional system bus devices. Some of the electrical specifications assume a specific 
effective termination resistance. See test conditions described with each specification. 
 
Due to the existence of termination on each of up to 4 processors in a Pentium® III Xeon™ processor at 700 MHz and 
900 MHz, the AGTL+ bus is typically not a daisy chain topology as in previous P6 Family processor systems. Like the 
Pentium® II Xeon™ processor, the Pentium® III Xeon™ processor at 700 MHz and 900 MHz timing specifications are 
defined to points internal to the processor cartridge. Analog signal simulation of the system bus is required when 
developing Pentium® III Xeon™ processor at 700 MHz and 900 MHz-based systems to ensure proper operation over all 
conditions.  

3.2  Power and Ground Pins 
 

By implementing an On Cartridge Voltage Regulator (OCVR), the Pentium® III Xeon™ processor at 700 MHz and 900 
MHz eliminates the need for high precision regulation from the flexible baseboard.  A Pentium® III Xeon™ processor at 
700 MHz and 900 MHz platform could be implemented to supply operating voltages of the processor die and of the L2 
cache die for compatibility with previous generations of the Pentium® III Xeon™ processor. These voltages may differ 
from each other. Note that the Pentium® III Xeon™ processor at 700 MHz and 900 MHz does not require a dedicated L2 
supply and that VID logic will assume L2 supply is not required. (Please refer to the VRM 8.3 specification for details). The 
Pentium® III Xeon™ processor at 700 MHz and 900 MHz FMB allows compatibility with previous Pentium® III Xeon™ 
processors. In an FMB that supports Pentium® III Xeon™ processor, there must be two groups of power inputs to support 
the voltage difference between the components in the package. The Pentium® III Xeon™ processor at 700 MHz and 900 
MHz will not use the voltage identification (VID) pins for L2 Cache (VID_L2), but a system that supports the previous 
generation of Pentium® III Xeon™ processors must use those pins to supply the correct voltages to the processor L2 
cache. 
 
In a FMB design, there are five pins defined on the package for core voltage identification (VID_CORE), and five pins 
defined on the package for L2 cache voltage identification (VID_L2). These pins specify the voltage required by the 
processor core and L2 cache respectively. A Pentium® III Xeon™ processor at 700 MHz and 900 MHz relies on the VID 
identification pins for the VCC_CORE required voltage level ONLY and does not require a separate L2 voltage supply. 
 
For signal integrity improvement and clean power distribution within the S.E.C. package, the Pentium® III Xeon™ 
processor at 700 MHz and 900 MHz FMB has 65 VCC (power) and 55 VSS (ground) inputs (see section 7.3 for a 
complete edge finger signal listing). The 65 VCC pins are further divided to provide the different voltage levels to the 
components. VCC_CORE inputs for the processor core account for 35 of the VCC pins, while 8 VTT inputs (1.5V) are 
used to provide an AGTL+ termination voltage to the processor.  The 20 VCC_L2 inputs are not connected on the 
Pentium® III Xeon™ processor at 700 MHz and 900 MHz). One Vcc_SMB pin is provided for use by the SMBus, and one 
Vcc_TAP. The Vcc_SMB, Vcc_TAP, Vcc_L2 (on previous versions of the Pentium® III Xeon™ only), and Vcc_CORE 
must remain electrically separated from each other. Vcc_SMB must be connected to a 3.3V power supply (even if the 
SMBus features are not used) in order for the processor to function properly. On the baseboard, all VCC_CORE pins 
must be connected to a voltage plane. Similarly, all VSS pins must be connected to a system ground plane.