Intel III Xeon 800 MHz 80526KZ800256 User Manual
Product codes
80526KZ800256
ELECTRICAL SPECIFICATIONS
21
8.
VCC_SMB must be connected to 3.3V power supply (even if the SMBus features are not used) in order for the processor to function
properly.
properly.
9.
A disabled processor OCVR draws approximately 46 mA at 2.8V V
CC
_
CORE
from the motherboard VRM. If your system needs to
maintain VRM regulation with a disabled processor (OCVR_EN inactive), the VRM output minimum load specification should be 46
mA or less.
mA or less.
10. The FMB specification is applicable to 2.8V OCVR processors where a VRM is used as the power source.
Table 7. AGTL+ Signal Groups, DC Specifications at the processor Core
Symbol Parameter
Min Max
Unit
Notes
V
IL
Input Low Voltage
-0.150
0.9
V
4,7
V
IH
Input
High
Voltage
1.15V
V
TT
V
1,4,7
R
ONN
nMOS On Resistance
12.5
Ohm
5, 6
R
ONP
pMOS On Resistance
85
Ohm
5, 8
V
OHTS
Output High Voltage Tri-state
V
TT
V
1, 4
I
L
Leakage
current
for
the
Inputs, Outputs and I/O
±15
µA
2,
3
NOTES:
1.
Processor core parameter correlated into a 25
Ω resistor to a V
TT
of 1.5V.
2. 0
≤ Vin ≤ 1.5 +3%.
3. 0
≤ Vout ≤ 2 +5%.
4.
The processor core drives high for only one clock cycle. It then drives low or tri-states its outputs. V
TT
is specified in Table 5.
5.
Not 100% tested. Specified by design characterization.
6. This
R
ON
specification corresponds to a V
OL_MAX
of 0.5V when taken into an effective 25
Ω
load to V
TT
of 1.5V.
7.
Vil/Vih are not guaranteed with respect to AC parameters.
8.
Specified under no load conditions at an I-V operating point of zero current and V=VTT conditions.
Table 8. CMOS, TAP, Clock and APIC Signal Groups, DC Specifications at the processor edge fingers
Symbol Parameter Min Max Unit
Notes
V
IL
Input Low Voltage
-0.150
0.7
V
6
V
IH
(PICCLK &
PWRGD only)
Input High Voltage
1.7
2.0
2.625
2.625
V
V
2.5V + 5% maximum, 7
2.5V + 5% maximum, 4, 5
V
OL
(APIC only)
Output Low Voltage
0.5
0.550
V
V
Parameter measured at 14mA
Parameter measured at 20mA
V
OH
Output High Voltage
2.625
V
All outputs are open-drain to 2.5V
+ 5%
I
LI
Input
Leakage
Current
±100 µA
1
I
LO
Output
Leakage
Current
±100 µA
2
Con I/O
Pin
Capacitance
25
pF
3
NOTES:
1. 0
≤ V
IN
≤ 2.625V.
2. 0
≤ V
OUT
≤ 2.625V.
3.
Total capacitance of processor core and voltage clamp device. Does not include cartridge trace capacitance. Applies to all CMOS,
TAP, Clock, and APIC signals except BCLK, PICCLK and PWRGOOD.
TAP, Clock, and APIC signals except BCLK, PICCLK and PWRGOOD.
4.
This parameter applies to PICCLK.
5.
This parameter applies to PWRDG.