Intel III Xeon 800 MHz 80526KZ800256 User Manual
Product codes
80526KZ800256
ELECTRICAL SPECIFICATIONS
22
6. Maximum
V
IL
at the processor core pin is specified as 2/3 V
TT
– 0.2V.
7. Minimum
V
IH
at the processor core pin is specified as 2/3 V
TT
+ 0.2V.
Table 9. SMBus Signal Group, DC Specifications at the processor edge fingers
Symbol Parameter
Min Max
Unit Notes
V
IL
Input Low Voltage
-0.3
0.3 x Vcc
SMB
V
V
IH
Input High Voltage
0.7 x Vcc
SMB
3.465
V 3.3V
+
5%
maximum
V
OL
Output
Low
Voltage
0.4
V
I
OL
Output Low Current
3
mA
Except SMBALERT#
I
OL2
Output Low Current
6
mA
SMBALERT# 1
I
LI
Input
Leakage
Current
10
µA
I
LO
Output Leakage Current
10
µA
NOTES:
1.
SMBALERT# is an open drain signal.
Table 10. OCVR Control Signals, DC Specifications at the processor edge fingers
Symbol Parameter
Min Max
Unit Notes
V
IL
OCVR_EN
Input Low Voltage
0.8
V
2, 3
V
IH
OCVR_EN
Input High Voltage
2.0
V
2, 3
V
OL
OCVR_OK
Output Low Voltage
0.4
V
-1.5mA max
V
OH
OCVR_OK
Output High Voltage
-
-
V
1
NOTES:
1.
Driver configured as open drain connected to 3.3V (Vcc_SMB) through a 10K
Ω resistor.
2.
Vih_max (absolute) = 5.25 VDC when the OCVR is powered.
3.
If the OCVR on the processor is not operating, such as at initial system power up or if there is no power input to the processor, the
input should be driven in such a way that no more than 20 mA can flow into the input (assuming it is connected to ground). This is
equivalent to using a 270
input should be driven in such a way that no more than 20 mA can flow into the input (assuming it is connected to ground). This is
equivalent to using a 270
Ω or higher pull-up resistor tied to a typical 5V supply as the only source for driving the input high.
3.11
AGTL+ System Bus Specifications
Table 11 below lists parameters controlled within the processor to be taken into consideration. A reference voltage
(VREF), derived on the processor cartridge from V
TT
, is used by the input buffers to determine the valid high and low
levels. VREF should be set to the same level for other AGTL+ logic using a voltage divider on the baseboard. It is
important that the baseboard impedance be held as tight as possible and that the intrinsic trace capacitance for the
AGTL+ signal group traces is known and well-controlled. See Layout Guidelines (section 2.4) for impedance
recommendations.
important that the baseboard impedance be held as tight as possible and that the intrinsic trace capacitance for the
AGTL+ signal group traces is known and well-controlled. See Layout Guidelines (section 2.4) for impedance
recommendations.