Intel III Xeon 800 MHz 80526KZ800256 User Manual
Product codes
80526KZ800256
ELECTRICAL SPECIFICATIONS
27
Table 16. System Bus AC Specifications (Reset Conditions
1
)
T# Parameter
Min
Max
Unit Figure
Notes
T16: Reset
Configuration
Signals
(A[14:05]#, BR0#, FLUSH#,
INIT#) Setup Time
4
BCLKs
Before de-assertion of
RESET
T17: Reset
Configuration
Signals
(A[14:05]#, BR0#, FLUSH#,
INIT#) Hold Time
2
20
BCLKs
After clock that de-
asserts RESET#
T18: Reset
Configuration
Signals
(A20M#, IGNNE#, LINT[1:0])
Setup Time
1
mS
Before de-assertion of
RESET#
T19: Reset
Configuration
Signals
(A20M#, IGNNE#, LINT[1:0])
Delay Time
5
BCLKs
After assertion of
RESET#
1
T20: Reset
Configuration
Signals
(A20M#, IGNNE#,
LINT[1:0]#) Hold Time
2 20
After clock that de-
asserts RESET#
NOTES:
1.
For a Reset, the clock ratio defined by these signals must be a safe value (their final or lower multiplier) within this delay unless
PWRGD is being driven inactive.
PWRGD is being driven inactive.
Table 17. System Bus AC Specifications (APIC Clock and APIC I/O) at the processor Core Pins
1
T# Parameter
Min
Max
Unit Figure
Notes
T21: PICCLK
Frequency
2.0 33.3 MHz
T22: PICCLK Period
30.0
500.0
nS
T23: PICCLK High Time
12.0
nS
T24: PICCLK Low Time
12.0
nS
T25: PICCLK Rise Time
0.25
3.0
nS
5
T26: PICCLK Fall Time
0.25
3.0
nS
5
T27: PICD[1:0] Setup Time
5.0
nS
2
T28: PICD[1:0] Hold Time
2.5
nS
2
T29A: PICD[1:0] Valid Delay
(Rising Edge)
(Rising Edge)
1.5 8.7
nS
Figure
5
2,3,4
T29B: PICD[1:0] Valid Delay
(Falling Edge)
(Falling Edge)
1.5
12.0
nS
Figure 5
2,3,4
NOTES:
1.
These specifications are tested during manufacturing.
2.
Referenced to PICCLK rising edge.
3.
For open drain signals, valid delay is synonymous with float delay.
4.
Valid delay timings for these signals are specified into a 150
Ω resistor to 2.5V.
5.
This data is specified at the processor core.