Intel III Xeon 800 MHz 80526KZ800256 User Manual
Product codes
80526KZ800256
APPENDIX
94
an external error signal (e.g. NMI) by system core logic. The processor will keep IERR# asserted until it is handled in
software, or with the assertion of RESET#, BINIT#, or INIT#.
software, or with the assertion of RESET#, BINIT#, or INIT#.
10.1.26 IGNNE# (I)
The IGNNE# (Ignore Numeric Error) signal is asserted to force the processor to ignore a numeric error and continue to
execute non-control floating-point instructions. If IGNNE# is deasserted, the processor generates an exception on a non-
control floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE
bit in control register 0 is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction, it must
be valid along with the TRDY# assertion of the corresponding I/O Write bus transaction.
During active RESET#, the processor begins sampling the A20M#, IGNNE# , and LINT[1:0] values to determine the ratio
of core-clock frequency to bus-clock frequency. See Table 1. On the active-to-inactive transition of RESET#, the
processor latches these signals and freezes the frequency ratio internally. System logic must then release these signals
for normal operation.
execute non-control floating-point instructions. If IGNNE# is deasserted, the processor generates an exception on a non-
control floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE
bit in control register 0 is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction, it must
be valid along with the TRDY# assertion of the corresponding I/O Write bus transaction.
During active RESET#, the processor begins sampling the A20M#, IGNNE# , and LINT[1:0] values to determine the ratio
of core-clock frequency to bus-clock frequency. See Table 1. On the active-to-inactive transition of RESET#, the
processor latches these signals and freezes the frequency ratio internally. System logic must then release these signals
for normal operation.
10.1.27 INIT# (I)
The INIT# (Initialization) signal, when asserted, resets integer registers inside all processors without affecting their internal
(L1 or L2) caches or floating-point registers. Each processor then begins execution at the power-on reset vector
configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion.
INIT# is an asynchronous signal and must connect the appropriate pins of all processor system bus agents.
If INIT# is sampled active on the active to inactive transition of RESET#, then the processor executes its Built-In Self-Test
(BIST).
(L1 or L2) caches or floating-point registers. Each processor then begins execution at the power-on reset vector
configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion.
INIT# is an asynchronous signal and must connect the appropriate pins of all processor system bus agents.
If INIT# is sampled active on the active to inactive transition of RESET#, then the processor executes its Built-In Self-Test
(BIST).
10.1.28 INTR - see LINT[0]
10.1.29 LINT[1:0] (I)
The LINT[1:0] (Local APIC Interrupt) signals must connect the appropriate pins of all APIC Bus agents, including all
processors and the core logic or I/O APIC component. When the APIC is disabled, the LINT0 signal becomes INTR, a
maskable interrupt request signal, and LINT1 becomes NMI, a non-maskable interrupt. INTR and NMI are backward
compatible with the signals of those names on the Pentium® processor. Both signals are asynchronous.
Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as
NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after reset, operation of these pins as LINT[1:0] is the
default configuration.
During active RESET#, the Pentium® III Xeon™ processor at 700 MHz begins sampling the A20M#, IGNNE#, and
LINT[1:0] values to determine the ratio of core-clock frequency to bus-clock frequency (See Table 1). On the active-to-
inactive transition of RESET#, the Pentium® III Xeon™ processor at 700 MHz samples these signals and latches the
frequency ratio internally. System logic must then release these signals for normal operation. The Pentium® III Xeon™
processor at 900 MHz does not sample the A20M#, IGNNE#, and LINT[1:] values at the de-assertion of the RESET#
signal, and will operate only with a 9:1 core/bus ratio.
processors and the core logic or I/O APIC component. When the APIC is disabled, the LINT0 signal becomes INTR, a
maskable interrupt request signal, and LINT1 becomes NMI, a non-maskable interrupt. INTR and NMI are backward
compatible with the signals of those names on the Pentium® processor. Both signals are asynchronous.
Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as
NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after reset, operation of these pins as LINT[1:0] is the
default configuration.
During active RESET#, the Pentium® III Xeon™ processor at 700 MHz begins sampling the A20M#, IGNNE#, and
LINT[1:0] values to determine the ratio of core-clock frequency to bus-clock frequency (See Table 1). On the active-to-
inactive transition of RESET#, the Pentium® III Xeon™ processor at 700 MHz samples these signals and latches the
frequency ratio internally. System logic must then release these signals for normal operation. The Pentium® III Xeon™
processor at 900 MHz does not sample the A20M#, IGNNE#, and LINT[1:] values at the de-assertion of the RESET#
signal, and will operate only with a 9:1 core/bus ratio.
10.1.30 LOCK# (I/O)
The LOCK# signal indicates to the system that a transaction must occur atomically. This signal must connect the
appropriate pins of all Pentium® III Xeon™ processor at 700 MHz and 900 MHz system bus agents. For a locked
sequence of transactions, LOCK# is asserted from the beginning of the first transaction end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the Pentium® III Xeon™ processor at 700 MHz and
900 MHz system bus, it will wait until it observes LOCK# deasserted. This enables symmetric agents to retain ownership
of the Pentium® III Xeon™ processor at 700 MHz and 900 MHz system bus throughout the bus locked operation and
ensure the atomicity of lock.
appropriate pins of all Pentium® III Xeon™ processor at 700 MHz and 900 MHz system bus agents. For a locked
sequence of transactions, LOCK# is asserted from the beginning of the first transaction end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the Pentium® III Xeon™ processor at 700 MHz and
900 MHz system bus, it will wait until it observes LOCK# deasserted. This enables symmetric agents to retain ownership
of the Pentium® III Xeon™ processor at 700 MHz and 900 MHz system bus throughout the bus locked operation and
ensure the atomicity of lock.