Intel III Xeon 800 MHz 80526KZ800256 User Manual
Product codes
80526KZ800256
APPENDIX
95
10.1.31 L2_SENSE
On Pentium® III Xeon™ processor at 500 MHz and 550 MHz cartridges, L2_SENSE is routed from the edge of the
connector pin B57 to the VL2 power plane. It allows monitoring the delivery of Vcc_L2 voltage at the L2 array device for
this processor. Since the Pentium® III Xeon™ processor at 700 MHz and 900 MHz does not have a separate L2 cache
voltage supply, this line is NOT used and is not recommended to be connected in systems based on the Pentium® III
Xeon™ processor at 700 MHz and 900 MHz only.
Systems that rely on remote sensing of Vcc_L2 need to guarantee this requirement is met at the VRM sense line
regardless of core feedback
connector pin B57 to the VL2 power plane. It allows monitoring the delivery of Vcc_L2 voltage at the L2 array device for
this processor. Since the Pentium® III Xeon™ processor at 700 MHz and 900 MHz does not have a separate L2 cache
voltage supply, this line is NOT used and is not recommended to be connected in systems based on the Pentium® III
Xeon™ processor at 700 MHz and 900 MHz only.
Systems that rely on remote sensing of Vcc_L2 need to guarantee this requirement is met at the VRM sense line
regardless of core feedback
.
10.1.32 OCVR_EN (I)
This signal is the output enable for the internal cartridge voltage regulator. Driving this Low will inactivate the outputs of
the OCVR. This is an open drain signal referenced high to +5V through a 10K
the OCVR. This is an open drain signal referenced high to +5V through a 10K
Ω
resistor within the cartridge to activate
the VRM when not driven low (this to satisfy legacy requirements). Refer to Figure 41 and Figure 42 For PWRGD
relationships at Power up.
relationships at Power up.
10.1.33 OCVR_OK(O)
This is an open drain compatible output from the On-Cartridge Voltage Regulator Module (OCVR) indicating that its
outputs are enabled and operating within specifications. This signal is referenced to Vcc_SMB (+3.3V) through a 10K
outputs are enabled and operating within specifications. This signal is referenced to Vcc_SMB (+3.3V) through a 10K
Ω
resistor, and should be used in conjunction with an equivalent signal from the host power system to generate the
CORE_PWRGD signals for the processor cores. Refer to Figure 41 and Figure 42 for PWRGD relationships at Power up.
PWRGD assertion must lag OCVR_OK assertion.
CORE_PWRGD signals for the processor cores. Refer to Figure 41 and Figure 42 for PWRGD relationships at Power up.
PWRGD assertion must lag OCVR_OK assertion.
10.1.34 NMI - See LINT[1]
10.1.35 PICCLK (I)
The PICCLK (APIC Clock) signal is a 2.5V tolerant input clock to the processor and core logic or I/O APIC that is required
for operation of all processors, core logic, and I/O APIC components on the APIC bus.
for operation of all processors, core logic, and I/O APIC components on the APIC bus.
10.1.36 PICD[1:0] (I/O)
The PICD[1:0] (APIC Data) signals are used for bi-directional serial message passing on the APIC bus, and must connect
the appropriate pins of all processors and core logic or I/O APIC components on the APIC bus.
the appropriate pins of all processors and core logic or I/O APIC components on the APIC bus.
10.1.37 PRDY# (O)
The PRDY (Probe Ready) signal is a processor output that is used by debug tools to determine processor debug
readiness.
readiness.
10.1.38 PREQ# (I)
The PREQ# (Probe Request) signal is used by debug tools to request debug operation of the processors.
10.1.39 PWREN[1:0] (I)
These 2 pins are tied directly together on the processor. They can be used to detect processor presence by applying a
voltage to one pin and observing it at the other. See 3.9 for the maximum rating for this signal.
voltage to one pin and observing it at the other. See 3.9 for the maximum rating for this signal.
10.1.40 PWRGOOD (I)
The (Power Good) signal is a 2.5V tolerant processor input. The processor requires this signal to be a clean indication
that the clocks and power supplies (Vcc_CORE, VCC_L2, VCC_TAP, VCC_SMB, VCC2.5) are stable and within their
that the clocks and power supplies (Vcc_CORE, VCC_L2, VCC_TAP, VCC_SMB, VCC2.5) are stable and within their