Intel 200 MHz FV8050366200 User Manual

E

30

5/23/97 10:47 AM    24318502.DOC

When two Pentium processors with MMX technology
are operating in dual processor mode, a "private bus"
exists to arbitrate for the processor bus and maintain
local cache coherency. The private bus consists of
two pinout changes:

1.  Five pins are added: PBREQ#, PBGNT#,

PHIT#, PHITM#, D/P#.

2. 

Ten output pins become I/O pins: ADS#, D/C#,
W/R#, M/IO#, CACHE#, LOCK#, HIT#, HITM#,
HLDA, SCYC, BE#4.

The new pins are given AC specifications of valid
delays at 0 pF, setup times and hold times. Simulate
with these parameters and their respective I/O buffer
models to guarantee that proper timings are met.

The AC specification gives input setup and hold
times for the ten signals that become I/O pins. These
setup and hold times must only be met when a dual
processor is present in the system.

The structure of the buffer models for the Pentium
processor with MMX technology and the Pentium
processor 133/150/166/200 are identical. Some of

the values of the components have changed to
reflect the minor manufacturing process and package
differences between the processors. The system
should see insignificant differences between the AC
behavior of the Pentium processor with MMX
technology and the Pentium processor
133/150/166/200.

Simulation of AC timings using the Pentium
processor with MMX technology buffer models is
recommended to ensure robust system designs. Pay
specific attention to the signal quality restrictions
imposed by 3.3V buffers.

Table 

9 provides stress ratings only. Functional

operation at the Absolute Maximum Ratings is not
implied or guaranteed. Functional operating
conditions are given in the AC and DC specification
tables.

Extended exposure to the maximum ratings may
affect device reliability. Furthermore, although the
Pentium processor with MMX technology contains
protective circuitry to resist damage from
electrostatic discharge, always take precautions to
avoid high static voltages or electric fields.

Storage Temperature

–65

150

°C

Case Temperature Under
Bias

–65

110

°C

V

CC3

V

CC3

 Supply Voltage with

respect to V

SS

–0.5

4.6

V

V

CC2

V

CC2

 Supply Voltage with

respect to V

SS

–0.5

3.7

V

V

IN3

3V Only Buffer DC Input
Voltage

–0.5

V

CC3

 +0.5 (not to

exceed V

CC3

 max)

V

Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. These are
stress ratings only. Operation beyond the DC specifications is not recommended or guaranteed and
extended exposure beyond the DC specifications may affect device reliability.