Intel 200 MHz FV8050366200 User Manual

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5/23/97 10:47 AM    24318502.DOC

specified at different voltages. See Table 10 for the
specification.

The display should show continuous sampling of the
voltage line, at 20 mV/div, and 500 ns/div with the
trigger point set to the center point of the range.
Slowly move the trigger to the high and low ends of
the specification, and verify that excursions beyond
these limits are not observed. There are no
allowances for crossing the high and low limits of the
voltage specification. For more information on
measurement techniques, see the 

Voltage

Guidelines for Pentium

®

 Processors with MMX™

Technology

 application note (Order Number 243186).

Liberal decoupling capacitance should be placed
near the Pentium processor with MMX technology.
The Pentium processor with MMX technology, when
driving its large address and data buses at high
frequencies, can cause transient power surges,
particularly when driving large capacitive loads.

Low inductance capacitors and interconnects are
recommended for best high frequency electrical
performance. Inductance can be reduced by
shortening circuit board traces between the Pentium
processor with MMX technology and decoupling
capacitors as much as possible. These capacitors
should be evenly distributed around each component
on the power plane. Capacitor values should be
chosen to ensure they eliminate both low and high
frequency noise components.

For the Pentium processor with MMX technology, the
power consumption can transition from a low level of
power to a much higher level (or high to low power)
very rapidly. A typical example would be entering or
exiting the Stop Grant State. Another example would
be executing a HALT instruction, causing the
Pentium processor with MMX technology to enter the
AutoHALT Power Down State, or transitioning from
HALT to the Normal State. All of these examples
may cause abrupt changes in the power being
consumed by the Pentium processor with MMX
technology. Note that the AutoHALT Power Down
feature is always enabled even when other power
management features are not implemented.

Bulk storage capacitors with a low Effective Series
Resistance (ESR) in the 10

Ω

 to 100

Ω

 range are

required to maintain a regulated supply voltage
during the interval between the time the current load
changes and the point that the regulated power

supply output can react to the change in load. In
order to reduce the ESR, it may be necessary to
place several bulk storage capacitors in parallel.

These capacitors should be placed near the Pentium
processor with MMX technology on both the V

CC2

and V

CC3

 plane to ensure that the supply voltage

stays within specified limits during changes in the
supply current during operation.

Detailed decoupling recommendations are provided
in the Flexible Motherboard Design Guidelines
application note (Order Number 243187)

The inputs and outputs of the Pentium processor with
MMX technology comply with the 3.3V JEDEC
standard levels. Both inputs and outputs are also
TTL-compatible, although the inputs cannot tolerate
voltage swings above the V

IN3

 (max) specification.

System support components which use TTL-
compatible inputs will interface to the Pentium
processor with MMX technology without extra logic.
This is because the Pentium processor drives
according to the 5V TTL specification (but not
beyond 3.3V).

For Pentium processor with MMX technology inputs,
the voltage must not exceed the 3.3V V

IN3

 (max)

specification. System support components can
consist of 3.3V devices or open-collector devices. In
an open-collector configuration, the external resistor
should be biased to V

CC3

.

All pins, including the CLK and PICCLK of the
Pentium processor with MMX technology, are 3.3V-
tolerant-only. If an 8259A interrupt controller is used,
for example, the system must provide level
converters between the 8259A and the Pentium
processor with MMX technology.

All NC and INC pins must remain unconnected.

For reliable operation, always connect unused inputs
to an appropriate signal level. Unused active low
inputs should be connected to V

CC3

. Unused active

high inputs should be connected to V

SS

 (ground).