Intel III Xeon 500 MHz 80525KX5001M User Manual
Product codes
80525KX5001M
Pentium
®
III Xeon™ Processor at 500 and 550 MHz
90
Datasheet
9.1.16
DBSY# (I/O)
The DBSY# (Data Bus Busy) signal is asserted by the agent responsible for driving data on the
Pentium
Pentium
III
Xeon processor system bus to indicate that the data bus is in use. The data bus is
released after DBSY# is deasserted. This signal must connect the appropriate pins on all Pentium
III
Xeon processor system bus agents.
9.1.17
DEFER# (I)
The DEFER# signal is asserted by an agent to indicate that a transaction cannot be guaranteed in-
order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or
I/O agent. This signal must connect the appropriate pins of all Pentium
order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or
I/O agent. This signal must connect the appropriate pins of all Pentium
III
Xeon processor system
bus agents.
9.1.18
DEP[7:0]# (I/O)
The DEP[7:0]# (Data Bus ECC Protection) signals provide optional ECC protection for the data
bus. They are driven by the agent responsible for driving D[63:00]#, and must connect the
appropriate pins of all Pentium
bus. They are driven by the agent responsible for driving D[63:00]#, and must connect the
appropriate pins of all Pentium
III
Xeon processor system bus agents which use them. The
DEP[7:0]# signals are enabled or disabled for ECC protection during power on configuration.
9.1.19
DRDY# (I/O)
The DRDY# (Data Ready) signal is asserted by the data driver on each data transfer, indicating
valid data on the data bus. In a multi-cycle data transfer, DRDY# may be deasserted to insert idle
clocks. This signal must connect the appropriate pins of all Pentium
valid data on the data bus. In a multi-cycle data transfer, DRDY# may be deasserted to insert idle
clocks. This signal must connect the appropriate pins of all Pentium
III
Xeon processor system bus
agents.
9.1.20
EMI
The EMI pins should be connected to baseboard or chassis ground through zero ohm resisters.
9.1.21
FERR# (O)
The FERR# (Floating-point Error) signal is asserted when the processor detects an unmasked
floating-point error. FERR# is similar to the ERROR# signal on the Intel387 coprocessor, and is
included for compatibility with systems using MS-DOS*-type floating-point error reporting.
floating-point error. FERR# is similar to the ERROR# signal on the Intel387 coprocessor, and is
included for compatibility with systems using MS-DOS*-type floating-point error reporting.
9.1.22
FLUSH# (I)
When the FLUSH# input signal is asserted, processors write back all data in the Modified state
from their internal caches and invalidate all internal cache lines. At the completion of this
operation, the processor issues a Flush Acknowledge transaction. The processor does not cache any
new data while the FLUSH# signal remains asserted.
from their internal caches and invalidate all internal cache lines. At the completion of this
operation, the processor issues a Flush Acknowledge transaction. The processor does not cache any
new data while the FLUSH# signal remains asserted.
FLUSH# is an asynchronous signal. However, to ensure recognition of this signal following an I/O
write instruction, it must be valid along with the TRDY# assertion of the corresponding I/O Write
bus transaction.
write instruction, it must be valid along with the TRDY# assertion of the corresponding I/O Write
bus transaction.