Intel III Xeon 500 MHz 80525KX5001M User Manual
Product codes
80525KX5001M
Pentium
®
III Xeon™ Processor at 500 and 550 MHz
92
Datasheet
During active RESET#, the Pentium
III
Xeon processor begins sampling the A20M#, IGNNE# ,
and LINT[1:0] values to determine the ratio of core-clock frequency to bus-clock frequency. See
. On the active-to-inactive transition of RESET#, the Pentium
III
Xeon processor latches
these signals and freezes the frequency ratio internally. System logic must then release these
signals for normal operation.
signals for normal operation.
9.1.27
INIT# (I)
The INIT# (Initialization) signal, when asserted, resets integer registers inside all processors
without affecting their internal (L1 or L2) caches or floating-point registers. Each processor then
begins execution at the power-on reset vector configured during power-on configuration. The
processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous
signal and must connect the appropriate pins of all Pentium
without affecting their internal (L1 or L2) caches or floating-point registers. Each processor then
begins execution at the power-on reset vector configured during power-on configuration. The
processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous
signal and must connect the appropriate pins of all Pentium
III
Xeon processor system bus agents.
If INIT# is sampled active on the active to inactive transition of RESET#, then the processor
executes its Built-In Self-Test (BIST).
executes its Built-In Self-Test (BIST).
9.1.28
INTR - see LINT0
9.1.29
LINT[1:0] (I)
The LINT[1:0] (Local APIC Interrupt) signals must connect the appropriate pins of all APIC Bus
agents, including all processors and the core logic or I/O APIC component. When the APIC is
disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1
becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals
of those names on the Pentium processor. Both signals are asynchronous.
agents, including all processors and the core logic or I/O APIC component. When the APIC is
disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1
becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals
of those names on the Pentium processor. Both signals are asynchronous.
Both of these signals must be software configured via BIOS programming of the APIC register
space to be used either as NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after
reset, operation of these pins as LINT[1:0] is the default configuration.
space to be used either as NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after
reset, operation of these pins as LINT[1:0] is the default configuration.
During active RESET#, the Pentium
III
Xeon processor begins sampling the A20M#, IGNNE# ,
and LINT[1:0] values to determine the ratio of core-clock frequency to bus-clock frequency. See
Table 1. On the active-to-inactive transition of RESET#, the Pentium
Table 1. On the active-to-inactive transition of RESET#, the Pentium
III
Xeon processor samples
these signals and latches the frequency ratio internally. System logic must then release these signals
for normal operation.
for normal operation.
9.1.30
LOCK# (I/O)
The LOCK# signal indicates to the system that a transaction must occur atomically. This signal
must connect the appropriate pins of all Pentium
must connect the appropriate pins of all Pentium
III
Xeon processor system bus agents. For a
locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction end
of the last transaction.
of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the Pentium
III
Xeon processor
system bus, it will wait until it observes LOCK# deasserted. This enables symmetric agents to
retain ownership of the Pentium
retain ownership of the Pentium
III
Xeon processor system bus throughout the bus locked operation
and ensure the atomicity of lock.