Intel III Xeon 500 MHz 80525KX5001M User Manual
Product codes
80525KX5001M
Pentium
®
III Xeon™ Processor at 500 and 550 MHz
Datasheet
97
9.1.52
STPCLK# (I)
The STPCLK# (Stop Clock) signal, when asserted, causes processors to enter a low power Stop
Grant state. The processor issues a Stop Grant Acknowledge transaction, and stops providing
internal clock signals to all processor core units except the bus and APIC units. The processor
continues to snoop bus transactions and service interrupts while in Stop Grant state. When
STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes execution.
The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input.
Grant state. The processor issues a Stop Grant Acknowledge transaction, and stops providing
internal clock signals to all processor core units except the bus and APIC units. The processor
continues to snoop bus transactions and service interrupts while in Stop Grant state. When
STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes execution.
The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input.
9.1.53
TCK (I)
The TCK (Test Clock) signal provides the clock input for the Pentium
III
Xeon processor Test Bus
(also known as the Test Access Port).
9.1.54
TDI (I)
The TDI (Test Data In) signal transfers serial test data into the Pentium
III
Xeon processor. TDI
provides the serial input needed for TAP support.
9.1.55
TDO (O)
The TDO (Test Data Out) signal transfers serial test data out of the Pentium
III
Xeon processor.
TDO provides the serial output needed for TAP support.
9.1.56
TEST_25_A62 (I)
The TEST_25_A62 signal must be connected to a 2. 5V power source through a 1-10 k
Ω
resistor
for proper processor operation.
9.1.57
TEST_VCC_CORE_XXX (I)
The TEST_VCC_CORE_XXX signals must be connected separately to V
CCCORE
via ~10 k
Ω
resistors.
9.1.58
THERMTRIP# (O)
This pin indicates a thermal overload condition (thermal trip). The processor protects itself from
catastrophic overheating by use of an internal thermal sensor. This sensor is set well above the
normal operating temperature to ensure that there are no false trips. The processor will immediately
stop all execution when the junction temperature exceeds approximately 135°C . This is signaled to
the system by the THERMTRIP# pin. Once activated, the signal remains latched, and the processor
stopped, until RESET# goes active. There is no hysteresis built into the thermal sensor itself. Once
the die temperature drops below the trip level, a RESET# pulse will reinitialize the processor and
execution will continue at the reset vector. If the temperature has not dropped below the trip level,
the processor will continue to drive THERMTRIP# and remain stopped regardless of the state of
RESET#.
catastrophic overheating by use of an internal thermal sensor. This sensor is set well above the
normal operating temperature to ensure that there are no false trips. The processor will immediately
stop all execution when the junction temperature exceeds approximately 135°C . This is signaled to
the system by the THERMTRIP# pin. Once activated, the signal remains latched, and the processor
stopped, until RESET# goes active. There is no hysteresis built into the thermal sensor itself. Once
the die temperature drops below the trip level, a RESET# pulse will reinitialize the processor and
execution will continue at the reset vector. If the temperature has not dropped below the trip level,
the processor will continue to drive THERMTRIP# and remain stopped regardless of the state of
RESET#.