Intel III Xeon 500 MHz 80525KX5001M User Manual
Product codes
80525KX5001M
Pentium
®
III Xeon™ Processor at 500 and 550 MHz
Datasheet
99
NOTES
1. All asynchronous input signals except PWRGOOD must be synchronous in FRC.
2. Synchronous assertion with active TDRY# ensures synchronization.
2. Synchronous assertion with active TDRY# ensures synchronization.
Table 49. Input Signals
1
Name
Active Level
Clock
Signal Group
Qualified
A20M#
Low
Asynch
CMOS Input
Always
2
BPRI#
Low
BCLK
AGTL+ Input
Always
BR[3:1]#
Low
BCLK
AGTL+ Input
Always
BCLK
High
—
System Bus Clock
Always
DEFER#
Low
BCLK
AGTL+ Input
Always
FLUSH#
Low
Asynch
CMOS Input
Always
2
IGNNE#
Low
Asynch
CMOS Input
Always
2
INIT#
Low
Asynch
CMOS Input
Always
2
INTR
High
Asynch
CMOS Input
APIC disabled mod
LINT[1:0]
High
Asynch
CMOS Input
APIC enabled mode
NMI
High
Asynch
CMOS Input
APIC disabled mod
PICCLK
High
—
APIC Clock
Always
PREQ#
Low
Asynch
CMOS Input
Always
PWRGOOD
High
Asynch
CMOS Input
Always
RESET#
Low
BCLK
AGTL+ Input
Always
RS[2:0]#
Low
BCLK
AGTL+ Input
Always
RSP#
Low
BCLK
AGTL+ Input
Always
SA[2:0]
High
SMBCLK
Power/Other
SMBCLK#
High
—
SMBus Clock
Always
SLP#
Low
Asynch
CMOS Input
During Stop Grant state
SMI#
Low
Asynch
CMOS Input
STPCLK#
Low
Asynch
CMOS Input
TCK
High
—
TAP Clock
TDI
High
TCK
TAP Input
TMS
High
TCK
TAP Input
TRST#
Low
Asynch
TAP Input
TRDY#
Low
BCLK
AGTL+ Input
WP
High
Asynch
SMBus Input