Intel III Xeon 550 MHz 80525KY5501M User Manual
Product codes
80525KY5501M
Pentium
®
III Xeon™ Processor at 500 and 550 MHz
96
Datasheet
signals to a Hi-Z state would cause ambiguity in the memory device address decode, possibly
resulting in the devices not responding, thus timing out or hanging the SMBus. As before, the “Z”
bit is the read/write bit for the serial bus transaction.
resulting in the devices not responding, thus timing out or hanging the SMBus. As before, the “Z”
bit is the read/write bit for the serial bus transaction.
For more information on the usage of these pins, see
.
9.1.46
SELFSB[1:0] (I/O)
Pentium
III
Xeon processors do not have a selectable system bus speed option. For Pentium
III
Xeon processors SELFSB0 should be left as an open. For systems which only support a 1 0 0MHz
system bus SELFSB1 should be grounded or left open. For systems which are intended to support
current processors with a 100MHz system bus and future processors with a 1 3 3MHz system bus
SELFSB1 may be connected to the baseboard logic which selects betwe en 100MHz a nd 133MHz.
For Pentium
system bus SELFSB1 should be grounded or left open. For systems which are intended to support
current processors with a 100MHz system bus and future processors with a 1 3 3MHz system bus
SELFSB1 may be connected to the baseboard logic which selects betwe en 100MHz a nd 133MHz.
For Pentium
III
Xeon processors and future 1 0 0MHz only processors this signal will pulled to
ground via a ~330
Ω
resistor. Future processors that will support a 133MHz system bus will leave
SELFSB1 open.
9.1.47
SLP# (I)
The SLP# (Sleep) signal, when asserted in Stop Grant state, causes processors to enter the Sleep
state. During Sleep state, the processor stops providing internal clock signals to all units, leaving
only the Phase-Locked Loop (PLL) still operating. Processors in this state will not recognize
snoops or interrupts. The processor will recognize only assertions of the SLP#, STPCLK#, and
RESET# signals while in Sleep state. If SLP# is deasserted, the processor exits Sleep state and
returns to Stop Grant state, restarting its internal clock signals to the bus and APIC processor core
units.
state. During Sleep state, the processor stops providing internal clock signals to all units, leaving
only the Phase-Locked Loop (PLL) still operating. Processors in this state will not recognize
snoops or interrupts. The processor will recognize only assertions of the SLP#, STPCLK#, and
RESET# signals while in Sleep state. If SLP# is deasserted, the processor exits Sleep state and
returns to Stop Grant state, restarting its internal clock signals to the bus and APIC processor core
units.
9.1.48
SMBALERT# (O)
SMBALERT# is an asynchronous interrupt line associated with the SMBus Thermal Sensor
device.
device.
9.1.49
SMBCLK (I)
The SMBCLK (SMBus Clock) signal is an input clock to the system management logic which is
required for operation of the system management features of the Pentium
required for operation of the system management features of the Pentium
III
Xeon processor. This
clock is asynchronous to other clocks to the processor.
9.1.50
SMBDAT (I/O)
The SMBDAT (SMBus DATa) signal is the data signal for the SMBus. This signal provides the
single-bit mechanism for transferring data between SMBus devices.
single-bit mechanism for transferring data between SMBus devices.
9.1.51
SMI# (I)
The SMI# (System Management Interrupt) signal is asserted asynchronously by system logic. On
accepting a System Management Interrupt, processors save the current state and enter System
Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins
program execution from the SMM handler.
accepting a System Management Interrupt, processors save the current state and enter System
Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins
program execution from the SMM handler.