Intel S2600JFQ BBS2600JFQ User Manual
Product codes
BBS2600JFQ
Intel®
Server Board S2600JF TPS
Product Architecture Overview
Revision 1.3
Intel order number G31608-004
13
3.3 Processor Function Overview
With the release of the Intel
®
Xeon
®
processor E5-2600 product family, several key system
components, including the CPU, Integrated Memory Controller (IMC), and Integrated IO Module
(IIO), have been combined into a single processor package and feature per socket; two Intel
(IIO), have been combined into a single processor package and feature per socket; two Intel
®
QuickPath Interconnect point-to-point links capable of up to 8.0 GT/s, up to 40 lanes of Gen 3
PCI Express* links capable of 8.0 GT/s, and 4 lanes of DMI2/PCI Express* Gen 2 interface with
a peak transfer rate of 5.0 GT/s. The processor supports up to 46 bits of physical address space
and 48-bit of virtual address space.
PCI Express* links capable of 8.0 GT/s, and 4 lanes of DMI2/PCI Express* Gen 2 interface with
a peak transfer rate of 5.0 GT/s. The processor supports up to 46 bits of physical address space
and 48-bit of virtual address space.
The following sections will provide an overview of the key processor features and functions that
help to define the performance and architecture of the server board. For more comprehensive
processor specific information, refer to the Intel
help to define the performance and architecture of the server board. For more comprehensive
processor specific information, refer to the Intel
®
Xeon
®
processor E5-2600 product family
documents listed in the Reference Documents section.
Processor Feature Details:
Up to eight execution cores
Each core supports two threads (Intel
Each core supports two threads (Intel
®
Hyper-Threading Technology), up to 16 threads
per socket
46-bit physical addressing and 48-bit virtual addressing
1GB large page support for server applications
A 32-KB instruction and 32-KB data first-level cache (L1) for each core
A 256KB shared instruction/data mid-level (L2) cache for each core
Up to 20MB last level cache (LLC) and up to 2.5MB per core instruction/data last level
1GB large page support for server applications
A 32-KB instruction and 32-KB data first-level cache (L1) for each core
A 256KB shared instruction/data mid-level (L2) cache for each core
Up to 20MB last level cache (LLC) and up to 2.5MB per core instruction/data last level
cache (LLC), shared among all cores
Supported Technologies:
Intel
®
Virtualization Technology (Intel
®
VT)
Intel
®
Virtualization Technology for Directed I/O (Intel
®
VT-d)
Intel
®
Virtualization Technology
Xeon
®
E5-2600
Processor Extensions
Intel
®
Trusted Execution Technology (Intel
®
TXT)
Intel
®
64 Architecture
Intel
®
Streaming SIMD Extensions 4.1 (Intel
®
SSE4.1)
Intel
®
Streaming SIMD Extensions 4.2 (Intel
®
SSE4.2)
Intel
®
Advanced Vector Extensions (Intel
®
AVX)
Intel
®
Hyper-Threading Technology
Execute Disable Bit
Intel
Intel
®
Turbo Boost Technology
Intel
®
Intelligent Power Technology
Data Direct I/O (DDIO)
Enhanced Intel
Enhanced Intel
®
SpeedStep Technology
Non-Transparent Bridge (NTB)