Intel S2600JFQ BBS2600JFQ User Manual
Product codes
BBS2600JFQ
Product Architecture Overview
Intel®
Server Board S2600JF TPS
Revision 1.3
Intel order number G31608-004
14
3.3.1
Intel
®
QuickPath Interconnect
The Intel
®
QuickPath Interconnect is a high speed, packetized, point-to-point interconnect used
in the processor. The narrow high-speed links stitch together processors in distributed shared
memory and integrated I/O platform architecture. It offers much higher bandwidth with low
latency. The Intel
memory and integrated I/O platform architecture. It offers much higher bandwidth with low
latency. The Intel
®
QuickPath Interconnect has an efficient architecture allowing more
interconnect performance to be achieved in real systems. It has a snoop protocol optimized for
low latency and high scalability, as well as packet and lane structures enabling quick
completions of transactions. Reliability, availability, and serviceability features (RAS) are built
into the architecture.
low latency and high scalability, as well as packet and lane structures enabling quick
completions of transactions. Reliability, availability, and serviceability features (RAS) are built
into the architecture.
The physical connectivity of each interconnect link is made up of twenty differential signal pairs
plus a differential forwarded clock. Each port supports a link pair consisting of two unidirectional
links to complete the connection between two components. This supports traffic in both
plus a differential forwarded clock. Each port supports a link pair consisting of two unidirectional
links to complete the connection between two components. This supports traffic in both
directions simultaneously. To facilitate flexibility and longevity, the interconnection is defined as
having five layers: Physical, Link, Routing, Transport, and Protocol.
having five layers: Physical, Link, Routing, Transport, and Protocol.
The Intel
®
QuickPath Interconnect includes a cache coherency protocol to keep the distributed
memory and caching structures coherent during system operation. It supports both low-latency
source snooping and a scalable home snoop behavior. The coherency protocol provides for
direct cache-to-cache transfers for optimal latency.
source snooping and a scalable home snoop behavior. The coherency protocol provides for
direct cache-to-cache transfers for optimal latency.
3.3.2
Integrated Memory Controller (IMC) and Memory Subsystem
QPI
PCIe
IMC -Memory
Controller
Core 0
L1
+
L
2
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ac
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L1
+
L
2
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ac
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L1
+
L
2
C
ac
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L1
+
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ac
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L1
+
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2
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ac
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L3
Cache
(2.5MB)
0
L3
Cache
(2.5MB)
1
L3
Cache
(2.5MB)
2
L3
Cache
(2.5MB)
3
Core 1
L1
+
L
2
C
ac
he
Core 2
L1
+
L
2
C
ac
he
Core 3
L1
+
L
2
C
ac
he
L3
Cache
(2.5MB)
7
L3
Cache
(2.5MB)
6
L3
Cache
(2.5MB)
5
L3
Cache
(2.5MB)
4
Core 7
Core 6
Core 5
Core 4
Figure 8. Processor with IMC Functional Block Diagram
Unbuffered DDR3 and registered DDR3 DIMMs
LR DIMM (Load Reduced DIMM) for buffered memory solutions demanding higher
LR DIMM (Load Reduced DIMM) for buffered memory solutions demanding higher
capacity memory subsystems
Independent channel mode or lockstep mode
Data burst length of eight cycles for all memory organization modes
Memory DDR3 data transfer rates of 800, 1066, 1333, and 1600 MT/s
64-bit wide channels plus 8-bits of ECC support for each channel
Data burst length of eight cycles for all memory organization modes
Memory DDR3 data transfer rates of 800, 1066, 1333, and 1600 MT/s
64-bit wide channels plus 8-bits of ECC support for each channel