Intel III Xeon 733 MHz 80526KZ733256 User Manual

 

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Due to the large number of transistors and high internal clock speeds, the processor is capable of generating large 
average current swings between low and full power states. This causes voltages on power planes to sag below their 
nominal values if bulk decoupling is not adequate. Care must be taken in the board design to ensure that the voltage 
provided to the processor remains within the specifications listed in Table 5. Failure to do so can result in timing violations 
or a reduced lifetime of the component. 

 
The power input should provide bulk capacitance with a low Effective Series Resistance (ESR) and the system designer 
must also control the interconnect resistance from the regulator (or VRM pins) to the SC330 connector. Simulation is 
required for first and second order characterization. Bulk decoupling for the large current swings when the part is 
powering on, or entering/exiting low power states, is provided on the voltage regulation module (VRM) defined in the VRM 
8.3 DC–DC Converter Design Guidelines. The input to VCC_CORE should be capable of delivering a recommended 
minimum dICCCORE/dt defined in Table 6 while maintaining the required tolerances defined in Table 5. 

3.3.2   LEVEL 2 CACHE DECOUPLING 
 

The Pentium® III Xeon™ processor at 700 MHz and 900 MHz does not require the VccL2 pins for power, however for 
systems that are designed to support this processor as well as previous Pentium® II Xeon™ and Pentium® III Xeon™ 
processors,  the regulator solutions need to implement and provide bulk capacitance with a low Effective Series 
Resistance (ESR) in order to meet the tolerance requirements for VCCL2 of previous processors. Use similar design 
practices as those recommended for VCC_CORE.  

 

The processor contains high frequency decoupling capacitance on the cartridge substrate; the system baseboard must 
provide bulk decoupling for proper AGTL+ bus operation. High frequency decoupling may be necessary at the SC330 
connector to further improve signal integrity if noise is introduced at the connector interface. 

3.4  Clock Frequencies and System Bus Clock Ratios 
 

The Pentium® III Xeon™ processor uses a clock ratio design in which the bus clock is multiplied by a ratio to produce the 
processors internal (“core”) clock. The Pentium® III Xeon™ processor at 700 MHz begins sampling A20M#, IGNNE#, 
LINT[0], and LINT[1] on the inactive-to-active transition of RESET# to determine the core-frequency to bus-frequency 
relationship, and the PLL immediately begins to lock on to the input clock. However, the Pentium® III Xeon™ processor at 
900 MHz ignores the logic states presented to the core/bus ratio pins at the de-assertion of the RESET# signal, and will 
operate only with a 9:1 core/bus ratio. On the active-to-inactive transition of RESET#, the Pentium® III Xeon™ processor 
at 700 MHz internally latches the inputs to allow the pins to be used for normal functionality. Effectively, these pins must 
meet a large setup time (1ms) to the active-to-inactive transition of RESET# (see RESET# and PWRGD relationship in 
Figure 41). These pins should then be held static for at least 2 bus clocks, but no longer than 20 bus clocks.