Intel III Xeon 733 MHz User Manuals

Table of Contents

• Product Features

  1
• 1. INTRODUCTION

  7
• 2. TERMINOLOGY

  8
  • 2.1 S.E.C. CARTRIDGE TERMINOLOGY

    8
• Additional terms referred to in this and other related documentation:

  9
  • State of Data

    9
  • References

    9
• 3. ELECTRICAL SPECIFICATIONS

  10
  • System Bus and VREF

    10
  • Power and Ground Pins

    10
  • Decoupling Guidelines

    12
    • 3.3.1 VCC_CORE

      12
    • LEVEL 2 CACHE DECOUPLING

      12
    • SYSTEM BUS AGTL+ DECOUPLING

      12
  • Clock Frequencies and System Bus Clock Ratios

    12
    • MIXING PROCESSORS OF DIFFERENT FREQUENCIES

      14
  • Voltage Identification

    14
  • System Bus Unused Pins and Test Pins

    17
  • System Bus Signal Groups

    17
    • ASYNCHRONOUS VS. SYNCHRONOUS FOR SYSTEM BUS SIGNALS

      18
  • Access Port (TAP) Connection

    18
  • Maximum Ratings

    19
  • Processor DC Specifications

    19
  • AGTL+ System Bus Specifications

    23
  • System Bus AC Specifications

    25
    • 26
      • 26
        • 26
          • Table€12. System Bus AC Specifications (Clock) at the processor Core Pins 1, 2, 3

            26
  • 4

    34
• 4. Signal Quality

  34
  • 4.1 Bus Clock Signal Quality Specifications

    34
  • 4.2 AGTL+ Signal Quality Specifications

    35
    • 4.2.2 AGTL+ Signal Quality Specifications

      35
    • 4.2.3 AGTL+ OVERSHOOT/UNDERSHOOT GUIDELINES

      35
      • 4.2.3.1 Overshoot/Undershoot Magnitude

        36
      • 4.2.3.2 Overshoot/Undershoot Pulse Duration

        36
      • 4.2.3.3 Overshoot/Undershoot Activity Factor

        36
      • 4.2.3.4 Determining if a System Meets the Overshoot/Undershoot Specifications

        36
• NOTES:

  38
  • 4.3 Non-GTL+ Signal Quality Specifications

    38
    • 4.3.1 2.5V Signal Overshoot/Undershoot Guidelines

      39
• Max Pulse Duration (nS)

  39
• NOTES:

  40
  • 40
    • 4.3.2 BCLK Overshoot/Undershoot Guidelines and Specifications

      40
    • 4.3.3 Measuring BCLK Overshoot/Undershoot

      40
    • 4.3.4 2.5V TOLERANT BUFFER RINGBACK SPECIFICATION

      41
    • 4.3.5 2.5V TOLERANT BUFFER SETTLING LIMIT GUIDELINE

      41
• 5. PROCESSOR FEATURES

  42
  • 5.1 Low Power States and Clock Control

    42
    • NORMAL STATE — STATE 1

      42
    • AUTO HALT POWER DOWN STATE — STATE 2

      42
    • STOP-GRANT STATE — STATE 3

      43
    • HALT/GRANT SNOOP STATE — STATE 4

      43
    • SLEEP STATE — STATE 5

      44
    • CLOCK CONTROL

      44
  • System Management Bus (SMBus) Interface

    44
    • PROCESSOR INFORMATION ROM

      45
    • SCRATCH EEPROM

      49
    • PROCESSOR INFORMATION ROM AND SCRATCH EEPROM SUPPORTED SMBUS TRANSACTIONS

      49
    • THERMAL SENSOR

      50
    • THERMAL SENSOR SUPPORTED SMBUS TRANSACTIONS

      51
    • THERMAL SENSOR REGISTERS

      52
      • Thermal Reference Registers

        52
      • Thermal Limit Registers

        52
      • Status Register

        53
      • Configuration Register

        53
      • Conversion Rate Register

        53
    • SMBus Device Addressing

      54
• 6. THERMAL SPECIFICATIONS AND DESIGN CONSIDERATIONS

  56
  • Thermal Specifications

    56
    • POWER DISSIPATION

      56
• NOTES:

  57
  • 58
    • PLATE FLATNESS SPECIFICATION

      58
  • Processor Thermal Analysis

    58
    • THERMAL SOLUTION PERFORMANCE

      58
    • THERMAL PLATE TO HEAT SINK INTERFACE MANAGEMENT GUIDE

      59
• NOTES:

  59
  • 59
    • MEASUREMENTS FOR THERMAL SPECIFICATIONS

      59
      • Plate Temperature Measurement

        59
• 7. MECHANICAL SPECIFICATIONS

  61
  • 7.1 Weight

    65
  • 7.2 Cartridge to Connector Mating Details

    65
  • 7.3 Substrate Edge Finger Signal Listing

    67
• 8. INTEGRATION TOOLS

  77
  • 8.1 In-Target Probe (ITP)

    77
    • 8.1.1 PRIMARY FUNCTION

      77
    • 8.1.2 DEBUG PORT CONNECTOR DESCRIPTION

      77
    • 8.1.3 KEEP OUT CONCERNS

      78
    • 8.1.4 ADDITIONAL INTEGRATION TOOL MECHANICAL KEEP OUTS

      78
    • 8.1.5 DEBUG PORT SIGNAL DESCRIPTIONS

      78
    • 8.1.6 DEBUG PORT SIGNAL NOTES

      81
      • 8.1.6.1 General Signal Quality Notes

        81
      • 8.1.6.2 Signal Note: DBRESET#

        81
      • 8.1.6.3 Signal Note: TDO and TDI

        81
      • 8.1.6.4 Signal Note: TCK and TMS

        82
    • 8.1.7 Using the TAP to Communicate to the processor

      83
  • 8.2 Logic Analyzer Interconnect (LAI) and Trace Capture Tool Considerations

    83
    • 8.2.1 LAI and Trace Capture Tool System Design Considerations

      83
    • 8.2.2 LAI and Trace Capture tool Mechanical Keep Outs

      83
• 9. BOXED PROCESSOR SPECIFICATIONS

  84
  • 9.1 Introduction

    84
  • 9.2 Mechanical Specifications

    84
    • 9.2.1 BOXED PROCESSOR HEATSINK DIMENSIONS

      86
    • 9.2.2 BOXED PROCESSOR HEATSINK WEIGHT

      86
    • 9.2.3 BOXED PROCESSOR RETENTION MECHANISM

      86
  • 9.3 Thermal Specifications

    87
    • 9.3.1 Boxed Processor Cooling Requirements

      87
    • 9.3.2 Boxed Processor Passive Heatsink Performance

      87
    • 9.3.2 Optional auxiliary fan attachment

      88
      • 9.3.2.1 Clearance recommendations for auxiliary fan

        88
      • 9.3.2.2 Fan power recommendations for auxiliary fan

        89
      • 9.3.2.3 Thermal evaluation for auxiliary fan

        90
• 10. APPENDIX

  91
  • 10.1 Alphabetical Signals Reference

    91
    • 10.1.1 A[35:03]# (I/O)

      91
    • 10.1.2 A20M# (I)

      91
    • 10.1.3 ADS# (I/O)

      91
    • 10.1.4 AERR# (I/O)

      91
    • 10.1.5 AP[1:0]# (I/O)

      91
    • 10.1.6 BCLK (I)

      91
    • 10.1.7 BERR# (I/O)

      92
    • 10.1.8 BINIT# (I/O)

      92
    • 10.1.9 BNR# (I/O)

      92
    • 10.1.10 BP[3:2]# (I/O)

      92
    • 10.1.11 BPM[1:0]# (I/O)

      92
    • 10.1.12 BPRI# (I)

      92
    • 10.1.13 BR0# (I/O), BR[3:1]# (I)

      92
    • 10.1.15 CORE_AN_SENSE (O)

      93
    • 10.1.16 D[63:00]# (I/O)

      93
    • 10.1.17 DBSY# (I/O)

      94
    • 10.1.18 DEFER# (I)

      94
    • 10.1.19 DEP[7:0]# (I/O)

      94
    • 10.1.20 DRDY# (I/O)

      94
    • 10.1.21 FERR# (O)

      94
    • 10.1.22 FLUSH# (I)

      94
    • 10.1.23 HIT# (I/O), HITM# (I/O)

      94
    • 10.1.24 HV_EN# (O)

      94
    • 10.1.25 IERR# (O)

      94
    • 10.1.26 IGNNE# (I)

      95
    • 10.1.27 INIT# (I)

      95
    • 10.1.28 INTR - see LINT[0]

      95
    • 10.1.29 LINT[1:0] (I)

      95
    • 10.1.30 LOCK# (I/O)

      95
    • 10.1.31 L2_SENSE

      96
    • 10.1.32 OCVR_EN (I)

      96
    • 10.1.33 OCVR_OK(O)

      96
    • 10.1.34 NMI - See LINT[1]

      96
    • 10.1.35 PICCLK (I)

      96
    • 10.1.36 PICD[1:0] (I/O)

      96
    • 10.1.37 PRDY# (O)

      96
    • 10.1.38 PREQ# (I)

      96
    • 10.1.39 PWREN[1:0] (I)

      96
    • 10.1.40 PWRGOOD (I)

      96
      • 97
        • 97
          • 97
            • 97
              • Figure€41. PWRGD Relationship at Power-On

                97
    • 10.1.41 REQ[4:0]# (I/O)

      98
    • 10.1.42 RESET# (I)

      99
    • 10.1.43 RP# (I/O)

      99
    • 10.1.44 RS[2:0]# (I)

      99
    • 10.1.45 RSP# (I)

      99
    • 10.1.46 SA[2:0] (I)

      99
    • 10.1.47 SELFSB0 (I) SELFSB1 (O)

      100
    • 10.1.48 SLP# (I)

      101
    • 10.1.49 SMBALERT# (O)

      101
    • 10.1.50 SMBCLK (I)

      101
    • 10.1.51 SMBDAT (I/O)

      102
    • 10.1.52 SMI# (I)

      102
    • 10.1.53 STPCLK# (I)

      102
    • 10.1.54 TCK (I)

      102
    • 10.1.55 TDI (I)

      102
    • 10.1.56 TDO (O)

      102
    • 10.1.57 TEST_2.5_[A23, A62, B27] (I)

      102
    • 10.1.58 THERMTRIP# (O)

      102
    • 10.1.59 TMS (I)

      102
    • 10.1.60 TRDY# (I)

      103
    • 10.1.61 TRST# (I)

      103
    • 10.1.62 VID_L2[4:0], VID_CORE[4:0] (O)

      103
    • 10.1.63 VIN_SENSE

      103
    • 10.1.64 WP (I)

      103
  • 10.2 Signal Summaries

    103