Intel III Xeon 733 MHz 80526KZ733256 User Manual

 

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VID_CORE[4:0] controls the voltage supply to the processor core and VID_L2[4:0] controls the voltage supply to the L2 
cache (in the case of the Pentium® II Xeon™ processor and Pentium® III Xeon™ processor at 500 MHz and 550 MHz). 
Both core and L2 use the same encoding as shown in Table 2. They are not driven signals, but are either an open circuit 
or a short circuit to VSS. The combination of opens and shorts defines the voltage required by the processor core (and L2 
cache for the Pentium® II Xeon™ processor and Pentium® III Xeon™ processor at 500 MHz and 550 MHz), the VID_L2 
lines on the Pentium® III Xeon™ processor at 700 MHz and 900 MHz are all left open (pulled high on the baseboard). 
The VID pins support variations in processor core voltages and L2 cache implementations among processors in the 
SC330 processor family. Table 2 shows the recommended range of values to support for both the processor core and the 
L2 cache. A ‘1’ in this table refers to an open pin and ‘0’ refers to a short to ground. The definition provided below is a 
superset of the definition previously defined for the Pentium® Pro processor (VID4 was not used by the Pentium® Pro 
processor) and is common to the Pentium® III Xeon™ processor at 700 MHz and 900 MHz (for VCC_CORE only), 
Pentium® II Xeon™ and previous Pentium® III Xeon™ processors. The power supply must supply the voltage that is 
requested or it must disable itself. 
 
To ensure the system is capable of supporting Pentium® III Xeon™ processor at 700 MHz and 900 MHz, Pentium® II 
Xeon™ processors and previous Pentium® III Xeon™ processors, a system should support those voltages indicated with 
a bold x in Table 2.