Intel III Xeon 733 MHz 80526KZ733256 User Manual
Product codes
80526KZ733256
APPENDIX
93
10.1.17 DBSY# (I/O)
The DBSY# (Data Bus Busy) signal is asserted by the agent responsible for driving data on the system bus to indicate
that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal must connect the appropriate
pins on all processor system bus agents.
that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal must connect the appropriate
pins on all processor system bus agents.
10.1.18 DEFER# (I)
The DEFER# signal is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion.
Assertion of DEFER# is normally the responsibility of all processor system bus agents.
Assertion of DEFER# is normally the responsibility of all processor system bus agents.
10.1.19 DEP[7:0]# (I/O)
The DEP[7:0]# (Data Bus ECC Protection) signals provide optional ECC protection for the data bus. They are driven by
the agent responsible for driving D[63:00]#, and must connect the appropriate pins of all processor system bus agents
which use them. The DEP[7:0]# signals are enabled or disabled for ECC protection during power on configuration.
the agent responsible for driving D[63:00]#, and must connect the appropriate pins of all processor system bus agents
which use them. The DEP[7:0]# signals are enabled or disabled for ECC protection during power on configuration.
10.1.20 DRDY# (I/O)
The DRDY# (Data Ready) signal is asserted by the data driver on each data transfer, indicating valid data on the data
bus. In a multi-cycle data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the
appropriate pins of all processor system bus agents.
bus. In a multi-cycle data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the
appropriate pins of all processor system bus agents.
10.1.21 FERR# (O)
The FERR# (Floating-point Error) signal is asserted when the processor detects an unmasked floating-point error. FERR#
is similar to the ERROR# signal on the Intel387™ coprocessor, and is included for compatibility with systems using DOS-
type floating-point error reporting.
is similar to the ERROR# signal on the Intel387™ coprocessor, and is included for compatibility with systems using DOS-
type floating-point error reporting.
10.1.22 FLUSH# (I)
When the FLUSH# input signal is asserted, processors write back all data in the Modified state from their internal caches
and invalidate all internal cache lines. At the completion of this operation, the processor issues a Flush Acknowledge
transaction. The processor does not cache any new data while the FLUSH# signal remains asserted.
and invalidate all internal cache lines. At the completion of this operation, the processor issues a Flush Acknowledge
transaction. The processor does not cache any new data while the FLUSH# signal remains asserted.
FLUSH# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction, it must
be valid along with the TRDY# assertion of the corresponding I/O Write bus transaction.
On the active-to-inactive transition of RESET#, each processor samples FLUSH# to determine its power-on configuration.
See
be valid along with the TRDY# assertion of the corresponding I/O Write bus transaction.
On the active-to-inactive transition of RESET#, each processor samples FLUSH# to determine its power-on configuration.
See
Pentium II Processor Developer’s Manual
for details.
10.1.23 HIT# (I/O), HITM# (I/O)
The HIT# (Snoop Hit) and HITM# (Hit Modified) signals convey transaction snoop operation results, and must connect the
appropriate pins of all processor system bus agents. Any such agent may assert both HIT# and HITM# together to
indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together.
appropriate pins of all processor system bus agents. Any such agent may assert both HIT# and HITM# together to
indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together.
10.1.24 HV_EN# (O)
The HV_EN# signal is used as a way of differentiating a 5V/12V version processor cartridge from a 2.8V version. HV_EN#
is tied to Vss (ground) on the 5V/12V version, and is high impedance (floating) on the 2.8V version. This is a reserved (no
connect) pin on previous versions of the Pentium® III Xeon™ processor.
is tied to Vss (ground) on the 5V/12V version, and is high impedance (floating) on the 2.8V version. This is a reserved (no
connect) pin on previous versions of the Pentium® III Xeon™ processor.
10.1.25 IERR# (O)
The IERR# (Internal Error) signal is asserted by a processor as the result of an internal error. Assertion of IERR# is
usually accompanied by a SHUTDOWN transaction on the system bus. This transaction may optionally be converted to
usually accompanied by a SHUTDOWN transaction on the system bus. This transaction may optionally be converted to