Intel III Xeon 733 MHz 80526KZ733256 User Manual
Product codes
80526KZ733256
APPENDIX
96
specifications. Clean implies that the signal will remain low (capable of sinking leakage current), without glitches, from the
time that the power supplies are turned on, until they come within specification. The signal must then transition
monotonically to a high (2.5V) state. Figure 41 illustrates the relationship of PWRGD to other system signals. PWRGD
can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of
PWRGD. It must also meet the minimum pulse width specification in Table 14 and be followed by a 8 mS RESET# pulse.
time that the power supplies are turned on, until they come within specification. The signal must then transition
monotonically to a high (2.5V) state. Figure 41 illustrates the relationship of PWRGD to other system signals. PWRGD
can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of
PWRGD. It must also meet the minimum pulse width specification in Table 14 and be followed by a 8 mS RESET# pulse.
The PWRGD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing
issues. It should be driven high throughout boundary scan operation.
issues. It should be driven high throughout boundary scan operation.
Current VRM 8.3 (on baseboard) specification requires VRM_PWRGD to be asserted when its output is within 12% of
nominal value. In the Pentium® III Xeon™ processor at 700 MHz and 900 MHz, PWRGD is logically ANDed with
OCVR_OK before being applied to the core (PWRGD_CORE). According to legacy datasheet documents, RESET#
negation is expected 1 mS after seeing PWRGD_CORE becoming valid by the processor core. The OCVR is not
expected to provide a valid OCVR_OK signal assertion within 13 mS of seeing 90% of its input voltage. The delay before
the assertion of OCVR_OK may cause a race condition between RESET# and the valid PWRGD_CORE that is seen at
the core. It is recommended to relax the deassertion of RESET# to meet this critical constrain. Careful analysis needs to
be done in existing platforms. Refer to Figure 41 and Figure 42 below for new timing relationship requirements.
OC VR_ O K
Vo u t (O CV R)
Vin (O CV R)
9 0 % o f Vin
No m ina l
No m ina l
2 .8 /5 /1 2 V
VCC_ CPU
RES E T#
VRM_ P WR G D
CPU_ P WR_ GD
1 mS
1 3 mS
0 .5 mS (max )
Figure 41. PWRGD Relationship at Power-On
NOTES:
1.
VCC_CORE must be applied to the OCVR input before OCVR_OK can become valid (even though it could be pulled high if the
VCC_SMB supply is turned on, see figure 41.
VCC_SMB supply is turned on, see figure 41.
2.
The OCVR_OK signal is not guaranteed to be valid until 0.5 mS (max) after Vin to the OCVR reaches 90% of it’s nominal value.
3.
Vin is the input to the OCVR (VCC_CORE).
4.
Vout is the output from the OCVR (VCC_CPU).