Intel G870 CM8062307260115 User Manual

12

Datasheet, Volume 1

• 1-Gb and 2-Gb DDR3 DRAM technologies are supported.
• Using 2-Gb device technologies, the largest memory capacity possible is 16 GB for 

UDIMMs (assuming Dual Channel Mode with a four dual rank unbuffered DIMM 
memory configuration)

• Up to 64 simultaneous open pages, 32 per channel (assuming 8 ranks of 8 bank 

devices)

• Command launch modes of 1n/2n
• Partial writes to memory using Data Mask (DM) signals
• Intel

®

 Fast Memory Access (Intel

®

 FMA)

— Just-in-Time Command Scheduling
— Command  Overlap
— Out-of-Order Scheduling

• The processor PCI Express* port(s) are fully-compliant to the PCI Express Base 

Specification, Revision 2.0.

• The processor with the desktop Intel 5 Series Chipset supports:

— One 16-lane PCI Express port intended for graphics attach
— Two 8-lane PCI Express ports (Only supported with Intel

®

 5 Series Chipset P55 

and P57 SKUs)

• The processor with the workstation Intel 3450 Chipset supports: 

— One 16-lane PCI Express port intended for graphics attach.
— Two 8-lane PCI Express ports for I/O.

• The processor with enhanced server Intel 3420 Chipset supports: 

— One 16-lane PCI Express port for graphics or I/O.
— Two 8-lane PCI Express ports for I/O.

• The processor with value server Intel 3400 Series Chipset supports:

— Two 8-lane PCI Express ports for I/O.

• PCI Express Port 0 is mapped to PCI Device 1.
• The port may negotiate down to narrower widths.

— Support for x16/x8/x4/x1 widths for a single PCI Express mode.

• 2.5 GT/s and 5.0 GT/s PCI Express frequencies are supported.
• Hierarchical PCI-compliant configuration mechanism for downstream devices.
• Traditional PCI style traffic (asynchronous snooped, PCI ordering).
• PCI Express extended configuration space. The first 256 bytes of configuration 

space aliases directly to the PCI Compatibility configuration space. The remaining 
portion of the fixed 4-KB block of memory-mapped space above that (starting at 
100h) is known as extended configuration space.

• PCI Express Enhanced Access Mechanism. Accessing the device configuration space 

in a flat memory mapped fashion.

• Automatic discovery, negotiation, and training of link out of reset.
• Traditional AGP style traffic (asynchronous non-snooped, PCI-X* Relaxed ordering).
• Peer segment destination posted write traffic (no peer-to-peer read traffic) in 

Virtual Channel 0:

— DMI -> PCI Express Port 0