User Manual (CM8062307260115)Table of Contents1 Introduction91.1 Processor Feature Details111.1.1 Supported Technologies111.2 Interfaces111.2.1 System Memory Support111.2.2 PCI Express*121.2.3 Direct Media Interface (DMI)131.2.4 Platform Environment Control Interface (PECI)141.2.5 Intel® HD Graphics141.2.6 Intel® Flexible Display Interface (Intel® FDI)141.3 Power Management Support151.3.1 Processor Core151.3.2 System151.3.3 Memory Controller151.3.4 PCI Express*151.4 Thermal Management Support151.5 Package151.6 Terminology151.7 Related Documents182 Interfaces192.1 System Memory Interface192.1.1 System Memory Technology Supported192.1.2 System Memory Timing Support202.1.3 System Memory Organization Modes212.1.3.1 Single-Channel Mode212.1.3.2 Dual-Channel Mode—Intel® Flex Memory Technology Mode212.1.4 Rules for Populating Memory Slots222.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)232.1.5.1 Just-in-Time Command Scheduling232.1.5.2 Command Overlap232.1.5.3 Out-of-Order Scheduling232.1.6 System Memory Pre-Charge Power Down Support Details232.2 PCI Express* Interface242.2.1 PCI Express* Architecture242.2.1.1 Transaction Layer252.2.1.2 Data Link Layer252.2.1.3 Physical Layer252.2.2 PCI Express* Configuration Mechanism262.2.3 PCI Express Port262.3 Direct Media Interface (DMI)272.3.1 DMI Error Flow272.3.2 Processor/PCH Compatibility Assumptions272.3.3 DMI Link Down272.4 Integrated Graphics272.4.1 3D and Video Engines for Graphics Processing282.4.1.1 3D Engine Execution Units (EUs)282.4.1.2 3D Pipeline282.4.1.3 Video Engine292.4.1.4 2D Engine292.4.2 Integrated Graphics Display312.4.2.1 Display Planes312.4.2.2 Display Pipes322.4.2.3 Display Ports322.4.3 Intel® Flexible Display Interface322.5 Platform Environment Control Interface (PECI)332.6 Interface Clocking332.6.1 Internal Clocking Requirements333 Technologies353.1 Intel® Virtualization Technology353.1.1 Intel® VT-x Objectives353.1.2 Intel® VT-x Features353.1.3 Intel® VT-d Objectives363.1.4 Intel® VT-d Features363.1.5 Intel® VT-d Features Not Supported373.2 Intel® Trusted Execution Technology (Intel® TXT)373.3 Intel® Hyper-Threading Technology383.4 Intel® Turbo Boost Technology383.5 New Instructions383.5.1 Advanced Encryption Standard New Instructions (AESNI)383.5.2 PCLMULQDQ Instruction384 Power Management394.1 ACPI States Supported394.1.1 System States394.1.2 Processor Core/Package Idle States394.1.3 Integrated Memory Controller States394.1.4 PCI Express* Link States404.1.5 Integrated Graphics States404.1.6 Interface State Combinations404.2 Processor Core Power Management414.2.1 Enhanced Intel® SpeedStep® Technology414.2.2 Low-Power Idle States414.2.3 Requesting Low-Power Idle States434.2.4 Core C-states444.2.4.1 Core C0 State444.2.4.2 Core C1/C1E State444.2.4.3 Core C3 State444.2.4.4 Core C6 State444.2.4.5 C-State Auto-Demotion454.2.5 Package C-States454.2.5.1 Package C0464.2.5.2 Package C1/C1E474.2.5.3 Package C3 State474.2.5.4 Package C6 State474.3 Integrated Memory Controller (IMC) Power Management484.3.1 Disabling Unused System Memory Outputs484.3.2 DRAM Power Management and Initialization484.3.2.1 Initialization Role of CKE484.3.2.2 Conditional Self-Refresh484.3.2.3 Dynamic Power Down Operation494.3.2.4 DRAM I/O Power Management494.4 PCI Express* Power Management494.5 Integrated Graphics Power Management504.5.1 Graphics Render C-State505 Thermal Management516 Signal Description536.1 System Memory Interface546.2 Memory Reference and Compensation566.3 Reset and Miscellaneous Signals566.4 PCI Express* Based Interface Signals586.5 DMI—Processor to PCH Serial Interface586.6 PLL Signals586.7 Intel® Flexible Display Interface Signals596.8 JTAG/ITP Signals596.9 Error and Thermal Protection606.10 Power Sequencing616.11 Processor Core Power Signals616.12 Graphics and Memory Core Power Signals636.13 Ground and NCTF636.14 Processor Internal Pull Up/Pull Down647 Electrical Specifications657.1 Power and Ground Lands657.2 Decoupling Guidelines657.2.1 Voltage Rail Decoupling657.3 Processor Clocking (BCLK[0], BCLK#[0])667.3.1 PLL Power Supply667.4 VCC Voltage Identification (VID)667.5 Graphics Voltage Identification (GFX_VID)677.6 Reserved or Unused Signals707.7 Signal Groups707.8 Test Access Port (TAP) Connection737.9 Absolute Maximum and Minimum Ratings737.10 DC Specifications747.10.1 Voltage and Current Specifications747.11 Platform Environmental Control Interface (PECI) DC Specifications827.11.1 DC Characteristics827.11.2 Input Device Hysteresis838 Processor Land and Signal Information858.1 Processor Land Assignments85Size: 692 KBPages: 102Language: EnglishOpen manual
User Manual (BX80623G870)Table of Contents2nd Generation Intel® Core™ Processor Family Desktop, Intel® Pentium® Processor Family Desktop, and Intel® Celeron® Processor Family Desktop1Contents3Tables6Revision History81 Introduction91.1 Processor Feature Details111.1.1 Supported Technologies111.2 Interfaces111.2.1 System Memory Support111.2.2 PCI Express*121.2.3 Direct Media Interface (DMI)131.2.4 Platform Environment Control Interface (PECI)141.2.5 Processor Graphics141.2.6 Intel® Flexible Display Interface (Intel® FDI)141.3 Power Management Support151.3.1 Processor Core151.3.2 System151.3.3 Memory Controller151.3.4 PCI Express*151.3.5 DMI151.3.6 Processor Graphics Controller151.4 Thermal Management Support151.5 Package161.6 Terminology161.7 Related Documents182 Interfaces192.1 System Memory Interface192.1.1 System Memory Technology Supported192.1.2 System Memory Timing Support212.1.3 System Memory Organization Modes212.1.3.1 Single-Channel Mode212.1.3.2 Dual-Channel Mode – Intel® Flex Memory Technology Mode212.1.4 Rules for Populating Memory Slots222.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)232.1.5.1 Just-in-Time Command Scheduling232.1.5.2 Command Overlap232.1.5.3 Out-of-Order Scheduling232.1.6 Memory Type Range Registers (MTRRs) Enhancement232.1.7 Data Scrambling232.2 PCI Express* Interface242.2.1 PCI Express* Architecture242.2.1.1 Transaction Layer252.2.1.2 Data Link Layer252.2.1.3 Physical Layer252.2.2 PCI Express* Configuration Mechanism262.2.3 PCI Express* Port262.2.4 PCI Express Lanes Connection272.3 Direct Media Interface (DMI)272.3.1 DMI Error Flow272.3.2 Processor/PCH Compatibility Assumptions272.3.3 DMI Link Down282.4 Processor Graphics Controller (GT)282.4.1 3D and Video Engines for Graphics Processing292.4.1.1 3D Engine Execution Units292.4.1.2 3D Pipeline292.4.1.3 Video Engine302.4.1.4 2D Engine302.4.2 Processor Graphics Display312.4.2.1 Display Planes312.4.2.2 Display Pipes322.4.2.3 Display Ports322.4.3 Intel® Flexible Display Interface322.4.4 Multi-Graphics Controller Multi-Monitor Support322.5 Platform Environment Control Interface (PECI)332.6 Interface Clocking332.6.1 Internal Clocking Requirements333 Technologies353.1 Intel® Virtualization Technology353.1.1 Intel® VT-x Objectives353.1.2 Intel® VT-x Features363.1.3 Intel® VT-d Objectives363.1.4 Intel® VT-d Features363.1.5 Intel® VT-d Features Not Supported373.2 Intel® Trusted Execution Technology (Intel® TXT)373.3 Intel® Hyper-Threading Technology383.4 Intel® Turbo Boost Technology383.4.1 Intel® Turbo Boost Technology Frequency393.4.2 Intel® Turbo Boost Technology Graphics Frequency393.5 Intel® Advanced Vector Extensions (AVX)403.6 Advanced Encryption Standard New Instructions (AES-NI)403.6.1 PCLMULQDQ Instruction403.7 Intel® 64 Architecture x2APIC414 Power Management434.1 Advanced Configuration and Power Interface (ACPI) States Supported444.1.1 System States444.1.2 Processor Core/Package Idle States444.1.3 Integrated Memory Controller States444.1.4 PCIe* Link States444.1.5 DMI States454.1.6 Processor Graphics Controller States454.1.7 Interface State Combinations454.2 Processor Core Power Management464.2.1 Enhanced Intel® SpeedStep® Technology464.2.2 Low-Power Idle States474.2.3 Requesting Low-Power Idle States484.2.4 Core C-states494.2.4.1 Core C0 State494.2.4.2 Core C1/C1E State494.2.4.3 Core C3 State494.2.4.4 Core C6 State494.2.4.5 C-State Auto-Demotion494.2.5 Package C-States504.2.5.1 Package C0514.2.5.2 Package C1/C1E514.2.5.3 Package C3 State524.2.5.4 Package C6 State524.3 IMC Power Management524.3.1 Disabling Unused System Memory Outputs524.3.2 DRAM Power Management and Initialization534.3.2.1 Initialization Role of CKE544.3.2.2 Conditional Self-Refresh544.3.2.3 Dynamic Power-down Operation554.3.2.4 DRAM I/O Power Management554.4 PCIe* Power Management554.5 DMI Power Management554.6 Graphics Power Management564.6.1 Intel® Rapid Memory Power Management (Intel® RMPM) (also known as CxSR)564.6.2 Intel® Graphics Performance Modulation Technology (Intel® GPMT)564.6.3 Graphics Render C-State564.6.4 Intel® Smart 2D Display Technology (Intel® S2DDT)564.6.5 Intel® Graphics Dynamic Frequency574.7 Thermal Power Management575 Thermal Management596 Signal Description616.1 System Memory Interface626.2 Memory Reference and Compensation636.3 Reset and Miscellaneous Signals646.4 PCI Express* Based Interface Signals656.5 Intel® Flexible Display Interface Signals656.6 DMI656.7 PLL Signals666.8 TAP Signals666.9 Error and Thermal Protection676.10 Power Sequencing676.11 Processor Power Signals686.12 Sense Pins686.13 Ground and NCTF686.14 Processor Internal Pull Up/Pull Down697 Electrical Specifications717.1 Power and Ground Lands717.2 Decoupling Guidelines717.2.1 Voltage Rail Decoupling717.3 Processor Clocking (BCLK[0], BCLK#[0])727.3.1 PLL Power Supply727.4 VCC Voltage Identification (VID)727.5 System Agent (SA) VCC VID767.6 Reserved or Unused Signals767.7 Signal Groups777.8 Test Access Port (TAP) Connection787.9 Storage Conditions Specifications797.10 DC Specifications807.10.1 Voltage and Current Specifications807.11 Platform Environmental Control Interface (PECI) DC Specifications867.11.1 PECI Bus Architecture867.11.2 DC Characteristics877.11.3 Input Device Hysteresis878 Processor Pin and Signal Information898.1 Processor Pin Assignments899 DDR Data Swizzling109Size: 1.82 MBPages: 112Language: EnglishOpen manual
