Intel G870 CM8062307260115 User Manual
Product codes
CM8062307260115
Power Management
48
Datasheet, Volume 1
4.3
Integrated Memory Controller (IMC) Power
Management
The main memory is power managed during normal operation and in low power ACPI
Cx states.
Cx states.
4.3.1
Disabling Unused System Memory Outputs
Any system memory (SM) interface signal that goes to a memory module connector in
which it is not connected to any actual memory devices (such as, DIMM connector is
unpopulated, or is single-sided) is tristated. The benefits of disabling unused SM signals
are:
which it is not connected to any actual memory devices (such as, DIMM connector is
unpopulated, or is single-sided) is tristated. The benefits of disabling unused SM signals
are:
• Reduced power consumption.
• Reduced possible overshoot/undershoot signal quality issues seen by the processor
• Reduced possible overshoot/undershoot signal quality issues seen by the processor
I/O buffer receivers caused by reflections from potentially un-terminated
transmission lines.
transmission lines.
When a given rank is not populated, the corresponding chip select and SCKE signals are
not driven.
not driven.
At reset, all rows must be assumed to be populated, until it can be proven that they are
not populated. This is due to the fact that when CKE is tristated with a DIMM present,
the DIMM is not ensured to maintain data integrity.
not populated. This is due to the fact that when CKE is tristated with a DIMM present,
the DIMM is not ensured to maintain data integrity.
4.3.2
DRAM Power Management and Initialization
The processor implements extensive support for power management on the SDRAM
interface. There are four SDRAM operations associated with the Clock Enable (CKE)
signals, which the SDRAM controller supports. The processor drives four CKE pins to
perform these operations.
interface. There are four SDRAM operations associated with the Clock Enable (CKE)
signals, which the SDRAM controller supports. The processor drives four CKE pins to
perform these operations.
4.3.2.1
Initialization Role of CKE
During power-up, CKE is the only input to the SDRAM that has its level recognized
(other than the DDR3 reset pin) once power is applied. It must be driven LOW by the
DDR controller to make sure the SDRAM components float DQ and DQS during power-
up. CKE signals remain LOW (while any reset is active) until the BIOS writes to a
configuration register. Using this method, CKE is ensured to remain inactive for much
longer than the specified 200 micro-seconds after power and clocks to SDRAM devices
are stable.
(other than the DDR3 reset pin) once power is applied. It must be driven LOW by the
DDR controller to make sure the SDRAM components float DQ and DQS during power-
up. CKE signals remain LOW (while any reset is active) until the BIOS writes to a
configuration register. Using this method, CKE is ensured to remain inactive for much
longer than the specified 200 micro-seconds after power and clocks to SDRAM devices
are stable.
4.3.2.2
Conditional Self-Refresh
Intel Rapid Memory Power Management (Intel RMPM) that conditionally places memory
into self-refresh in the C3 and C6 low power states, is based on the graphics/display
state (if internal graphics is being used).
into self-refresh in the C3 and C6 low power states, is based on the graphics/display
state (if internal graphics is being used).
When entering the Suspend-to-RAM (STR) state, the processor core flushes pending
cycles and then enters all SDRAM ranks into self refresh. In STR, the CKE signals
remain LOW so the SDRAM devices perform self refresh.
cycles and then enters all SDRAM ranks into self refresh. In STR, the CKE signals
remain LOW so the SDRAM devices perform self refresh.
The target behavior is to enter self-refresh for the package C3 and C6 states as long as
there are no memory requests to service. The target usage is shown in
there are no memory requests to service. The target usage is shown in
.