Intel G870 CM8062307260115 User Manual
Product codes
CM8062307260115
Electrical Specifications
82
Datasheet, Volume 1
7.11
Platform Environmental Control Interface (PECI)
DC Specifications
PECI is an Intel proprietary interface that provides a communication channel between
Intel processors and chipset components to external thermal monitoring devices. The
processor contains a Digital Thermal Sensor (DTS) that reports a relative die
temperature as an offset from Thermal Control Circuit (TCC) activation temperature.
Temperature sensors located throughout the die are implemented as analog-to-digital
converters calibrated at the factory. PECI provides an interface for external devices to
read the DTS temperature for thermal management and fan speed control. For the
PECI command set supported by the processor, refer to the appropriate processor
Thermal and Mechanical Specifications and Design Guidelines for additional information
(see
Intel processors and chipset components to external thermal monitoring devices. The
processor contains a Digital Thermal Sensor (DTS) that reports a relative die
temperature as an offset from Thermal Control Circuit (TCC) activation temperature.
Temperature sensors located throughout the die are implemented as analog-to-digital
converters calibrated at the factory. PECI provides an interface for external devices to
read the DTS temperature for thermal management and fan speed control. For the
PECI command set supported by the processor, refer to the appropriate processor
Thermal and Mechanical Specifications and Design Guidelines for additional information
(see
).
7.11.1
DC Characteristics
The PECI interface operates at a nominal voltage set by V
TT
. The set of DC electrical
specifications shown in
is used with devices normally operating from a V
TT
interface supply. V
TT
nominal levels will vary between processor families. All PECI
devices will operate at the V
TT
level determined by the processor installed in the
system. For specific nominal V
TT
levels, refer to
.
Notes:
1.
V
TT
supplies the PECI interface. PECI behavior does not affect V
TT
min/max specifications.
2.
The leakage specification applies to powered devices on the PECI bus.
Table 7-13. PECI DC Electrical Limits
Symbol
Definition and Conditions
Min
Max
Units
Notes
1
V
in
Input Voltage Range
-0.150
V
TT
V
V
hysteresis
Hysteresis
0.1 * V
TT
N/A
V
V
n
Negative-Edge Threshold Voltage
0.275 * V
TT
0.500 * V
TT
V
V
p
Positive-Edge Threshold Voltage
0.550 * V
TT
0.725 * V
TT
V
I
source
High-Level Output Source
(V
(V
OH
= 0.75 * V
TT
)
-6.0
N/A
mA
I
sink
Low-Level Output Sink
(V
(V
OL
= 0.25 * V
TT
)
0.5
1.0
mA
I
leak+
High Impedance State Leakage to
V
TT
(V
leak
= V
OL
)
N/A
100
µA
2
I
leak-
High Impedance Leakage to GND
(V
leak
= V
OH
)
N/A
100
µA
2
C
bus
Bus Capacitance per Node
N/A
10
pF
V
noise
Signal Noise Immunity above
300 MHz
0.1 * V
TT
N/A
V
p-p