Intel G640T CM8062301002204 User Manual

108

Datasheet, Volume 2

System software can modify bits in this register, but the device is prohibited from doing 
so.

If the device writes the same message multiple times, only one of those messages is 
ensured to be serviced. If all of them must be serviced, the device must not generate 
the same message again until the driver services the earlier one.

15:8

RO

0h

7

RO

0b

Uncore

64-bit Address Capable (B64AC)
Hardwired to 0 to indicate that the function does not implement 

the upper 32 bits of the Message Address register and is incapable 

of generating a 64-bit memory address. 
This may need to change in future implementations when 

addressable system memory exceeds the 32b/4GB limit. 

6:4

RW

000b

Uncore

Multiple Message Enable (MME)
System software programs this field to indicate the actual number 

of messages allocated to this device. This number will be equal to 

or less than the number actually requested. 
The encoding is the same as for the MMC field below. 

3:1

RO

000b

Uncore

Multiple Message Capable (MMC)
System software reads this field to determine the number of 

messages being requested by this device. The encoding for the 

number of messages requested is:
000 = 1
All of the following are reserved in this implementation: 
001 = 2
010 = 4
011 = 8
100 = 16
101 = 32
110 = Reserved 
111 = Reserved

0

RW

0b

Uncore

MSI Enable (MSIEN)
Controls the ability of this device to generate MSIs. 
0 = MSI will not be generated. 

1 = MSI will be generated when we receive PME messages. INTA 

will not be generated and INTA Status (PCISTS1[3]) will not 

be set.