Intel G640T CM8062301002204 User Manual

Product codes
CM8062301002204
Page of 296
Datasheet, Volume 2
169
Processor Configuration Registers
2.10.34 PEG_CAP—PCI Express-G Capabilities Register
This register indicates PCI Express device capabilities.
2.10.35 DCAP—Device Capabilities Register
This register indicates PCI Express device capabilities.
B/D/F/Type:
0/6/0/PCI
Address Offset:
A2–A3h
Reset Value:
0142h
Access:
RO, RW-O
Size:
16 bits
BIOS Optimal Default
0h
Bit
Attr
Reset 
Value
RST/
PWR
Description
15:14
RO
0h
Reserved
13:9
RO
00h
Uncore
Interrupt Message Number (IMN)
Not Applicable or Implemented. Hardwired to 0.
8
RW-O
1b
Uncore
Slot Implemented (SI)
0 = The PCI Express Link associated with this port is connected to 
an integrated component or is disabled.
1 = The PCI Express Link associated with this port is connected to 
a slot.
BIOS Requirement: This field must be initialized appropriately if 
a slot connection is not implemented. 
7:4
RO
4h
Uncore
Device/Port Type (DPT)
Hardwired to 4h to indicate root port of PCI Express Root Complex.
3:0
RO
2h
Uncore
PCI Express Capability Version (PCIECV)
Hardwired to 2h to indicate compliance to the PCI Express 
Capabilities Register Expansion ECN.
B/D/F/Type:
0/6/0/PCI
Address Offset:
A4–A7h
Reset Value:
0000_8000h
Access:
RO, RW-O
Size:
32 bits
BIOS Optimal Default
0000000h
Bit
Attr
Reset 
Value
RST/
PWR
Description
31:16
RO
0h
Reserved
15
RO
1b
Uncore
Role Based Error Reporting (RBER)
Indicates that this device implements the functionality defined in 
the Error Reporting ECN as required by the PCI Express 1.1 
specification.
14:6
RO
0h
Reserved
5
RO
0b
Uncore
Extended Tag Field Supported (ETFS)
Hardwired to indicate support for 5-bit Tags as a Requestor. 
4:3
RO
00b
Uncore
Phantom Functions Supported (PFS)
Not Applicable or Implemented. Hardwired to 0.
2:0
RW-O
000b
Uncore
Max Payload Size (MPS)
Default indicates 128B maximum supported payload for 
Transaction Layer Packets (TLP.).