Intel G640T CM8062301002204 User Manual
Product codes
CM8062301002204
Datasheet, Volume 2
171
Processor Configuration Registers
2.10.37 DSTS—Device Status Register
This register reflects status corresponding to controls in the Device Control register.
The error reporting bits are in reference to errors detected by this device, not errors
messages received across the link.
The error reporting bits are in reference to errors detected by this device, not errors
messages received across the link.
B/D/F/Type:
0/6/0/PCI
Address Offset:
AA–ABh
Reset Value:
0000h
Access:
RO, RW1C
Size:
16 bits
BIOS Optimal Default
000h
Bit
Attr
Reset
Value
RST/
PWR
Description
15:6
RO
0h
Reserved
5
RO
0b
Uncore
Transactions Pending (TP)
0 = All pending transactions (including completions for any
0 = All pending transactions (including completions for any
outstanding non-posted requests on any used virtual channel)
have been completed.
1 = Indicates that the device has transaction(s) pending
(including completions for any outstanding non-posted
requests for all used Traffic Classes).
Not Applicable or Implemented. Hardwired to 0.
4
RO
0h
Reserved
3
RW1C
0b
Uncore
Unsupported Request Detected (URD)
When set, this bit indicates that the Device received an
When set, this bit indicates that the Device received an
Unsupported Request. Errors are logged in this register regardless
of whether error reporting is enabled or not in the Device Control
Register.
Additionally, the Non-Fatal Error Detected bit or the Fatal Error
Additionally, the Non-Fatal Error Detected bit or the Fatal Error
Detected bit is set according to the setting of the Unsupported
Request Error Severity bit. In production systems setting the Fatal
Error Detected bit is not an option as support for AER will not be
reported.
2
RW1C
0b
Uncore
Fatal Error Detected (FED)
When set, this bit indicates that fatal error(s) were detected.
When set, this bit indicates that fatal error(s) were detected.
Errors are logged in this register regardless of whether error
reporting is enabled or not in the Device Control register.
When Advanced Error Handling is enabled, errors are logged in this
When Advanced Error Handling is enabled, errors are logged in this
register regardless of the settings of the uncorrectable error mask
register.
1
RW1C
0b
Uncore
Non-Fatal Error Detected (NFED)
When set, this bit indicates that non-fatal error(s) were detected.
When set, this bit indicates that non-fatal error(s) were detected.
Errors are logged in this register regardless of whether error
reporting is enabled or not in the Device Control register.
When Advanced Error Handling is enabled, errors are logged in this
When Advanced Error Handling is enabled, errors are logged in this
register regardless of the settings of the uncorrectable error mask
register.
0
RW1C
0b
Uncore
Correctable Error Detected (CED)
When set, this bit indicates that correctable error(s) were
When set, this bit indicates that correctable error(s) were
detected. Errors are logged in this register regardless of whether
error reporting is enabled or not in the Device Control register.
When Advanced Error Handling is enabled, errors are logged in this
When Advanced Error Handling is enabled, errors are logged in this
register regardless of the settings of the correctable error mask
register.