Intel G640T CM8062301002204 User Manual

Product codes
CM8062301002204
Page of 296
Datasheet, Volume 2
183
Processor Configuration Registers
2.11.4
VC0RCAP—VC0 Resource Capability Register
B/D/F/Type:
0/6/0/MMR
Address Offset:
110–113h
Reset Value:
0000_0001h
Access:
RO
Size:
32 bits
BIOS Optimal Default
00h
Bit
Attr
Reset 
Value
RST/
PWR
Description
31:24
RO
00h
Uncore
Reserved for Port Arbitration Table Offset (PATO)
23
RO
0h
Reserved
22:16
RO
00h
Uncore
Reserved for Maximum Time Slots (MTS) 
15
RO
0b
Uncore
Reject Snoop Transactions (RSNPT)
0 = Transactions with or without the No Snoop bit set within the 
TLP header are allowed on this VC.
1 = Any transaction for which the No Snoop attribute is applicable 
but is not Set within the TLP Header will be rejected as an 
Unsupported Request
14:8
RO
0h
Reserved
7:0
RO
01h
Uncore
Port Arbitration Capability (PAC)
Indicates types of Port Arbitration supported by the VC resource. 
This field is valid for all Switch Ports, Root Ports that support peer- 
to-peer traffic, and RCRBs, but not for PCI Express Endpoint 
devices or Root Ports that do not support peer-to-peer traffic.
Each bit location within this field corresponds to a Port Arbitration 
Capability defined below. When more than one bit in this field is 
set, it indicates that the VC resource can be configured to provide 
different arbitration services.
Software selects among these capabilities by writing to the Port 
Arbitration Select field (see below).
Defined bit positions are:
Bit 0
Non-configurable hardware-fixed arbitration scheme, 
such as, Round Robin (RR)
Bit 1
Weighted Round Robin (WRR) arbitration with 32 phases
Bit 2
WRR arbitration with 64 phases
Bit 3
WRR arbitration with 128 phases
Bit 4
Time-based WRR with 128 phases
Bit 5
WRR arbitration with 256 phases
Bits 6–7 Reserved
Processor only supported arbitration indicates "Non-configurable 
hardware-fixed arbitration scheme".