Intel G640T CM8062301002204 User Manual
Product codes
CM8062301002204
Datasheet, Volume 2
217
Processor Configuration Registers
2.16.4
PM_SREF_config—Self Refresh Configuration Register
This self refresh mode control register defines if and when DDR can go into SR.
B/D/F/Type:
0/0/0/MCHBAR_MCMAIN
Address Offset:
5060–5063h
Reset Value:
0001_00FFh
Access:
RW-L
Size:
32 bits
BIOS Optimal Default
0000h
Bit
Attr
Reset
Value
RST/
PWR
Description
31:15
RO
0h
Reserved
16
RW-L
1
Uncore
Self-refresh Enable
This control bit is an INTEL RESERVED register. It is for test and
This control bit is an INTEL RESERVED register. It is for test and
debug purposes only. This bit enables or disables self-refresh
mechanism.
15:0
RW-L
00FFh
Uncore
Idle timer init value (Idle_timer)
This value is used when the “SREF_enable” field is set. It defines
This value is used when the “SREF_enable” field is set. It defines
the # of cycles, that there should not be any transaction to enter
self-refresh. It is programmable 1 to 64K–1. In DCLK=800 it
determines time of up to 82 us.