Intel G640T CM8062301002204 User Manual

Datasheet, Volume 2

219

This register defines the power contribution of each command - ACT+PRE, CAS-read 
and CAS write. Assumption is that the ACT is always followed by a PRE (although not 
immediately), and REF commands are issued in a fixed rate and there is no need to 
count them. The register has three 8-bit fields.

This register defines the BW throttling at temperature.

Note that the field “BW_limit_tf may not be changed in run-time. Other fields may be 
changed in run-time. 

31:24

RO

0h

23:16

RW-LV

00h

Uncore

15:8

RW-LV

00h

Uncore

7:0

RW-LV

00h

Uncore

(PWR_RAS_PRE)
Power contribution of RAS command and PRE command. The value 

should be the sum of the two commands, assuming that each RAS 

command for a given page is followed by a PRE command to the 

same page in the near future.

31:24

RW-L

FFh

Uncore

BW limit when rank is hot (BW_limit_hot)
The number of transactions allowed per rank when status of rank is 

hot. 
Range = 0–255h 

23:16

RW-L

FFh

Uncore

BW limit when rank is warm (BW_limit_warm)
The number of transactions allowed per rank when status of rank is 

warm. 
Range = 0–255h 

15:10

RO

0h

9:0

RW-L

3FFh

Uncore

BW limit time frame (BW_limit_tf)
Time frame in which the BW limit is enforced, in DCLK cycles. 

Range = 1–1023h
Note that the field “BW_limit_tf may not be changed in run-time.