Intel G640T CM8062301002204 User Manual
Product codes
CM8062301002204
Processor Configuration Registers
238
Datasheet, Volume 2
2.18.13 AFLOG_REG—Advanced Fault Log Register
This register specifies the base address of the memory-resident fault-log region. This
register is treated as RsvdZ for implementations not supporting advanced translation
fault logging (AFL field reported as 0 in the Capability register).
register is treated as RsvdZ for implementations not supporting advanced translation
fault logging (AFL field reported as 0 in the Capability register).
B/D/F/Type:
0/0/0/GFXVTBAR
Address Offset:
58–5Fh
Reset Value:
0000_0000_0000_0000h
Access:
RO
Size:
64 bits
BIOS Optimal Default
000h
Bit
Attr
Reset
Value
RST/
PWR
Description
63:12
RO
00000000
00000h
Uncore
Fault Log Address (FLA)
This field specifies the base of 4 KB aligned fault-log region in
This field specifies the base of 4 KB aligned fault-log region in
system memory. Hardware ignores and does not implement bits
63:HAW, where HAW is the host address width.
Software specifies the base address and size of the fault log region
Software specifies the base address and size of the fault log region
through this register, and programs it in hardware through the SFL
field in the Global Command register. When implemented, reads of
this field return the value that was last programmed to it.
11:9
RO
0h
Uncore
Fault Log Size (FLS)
This field specifies the size of the fault log region pointed by the
This field specifies the size of the fault log region pointed by the
FLA field. The size of the fault log region is 2^X * 4KB, where X is
the value programmed in this register.
When implemented, reads of this field return the value that was
When implemented, reads of this field return the value that was
last programmed to it.
8:0
RO
0h
Reserved