Intel G640T CM8062301002204 User Manual

240

Datasheet, Volume 2

This register sets up the base address of DMA-protected low-memory region below 
4 GB. This register must be set up before enabling protected memory through 
PMEN_REG, and must not be updated when protected memory regions are enabled.

This register is always treated as RO for implementations not supporting protected low 
memory region (PLMR field reported as Clear in the Capability register).

The alignment of the protected low memory region base depends on the number of 
reserved bits (N:0) of this register. Software may determine N by writing all 1s to this 
register, and finding the most significant zero bit position with 0 in the value read back 
from the register. Bits N:0 of this register is decoded by hardware as all 0s.

Software must setup the protected low memory region below 4 GB.

Software must not modify this register when protected memory regions are enabled 
(PRS field Set in PMEN_REG).

 

31:20

RW

000h

Uncore

Protected Low-Memory Base (PLMB)
This register specifies the base of protected low-memory region in 

system memory.

19:0

RO

0h