Intel G640T CM8062301002204 User Manual

Product codes

CM8062301002204

Processor Configuration Registers

264

Datasheet, Volume 2

2.21

Default PEG/DMI VT-d Remapping Engine

Registers

Table 2-23

lists the registers arranged by address offset. Register bit descriptions are in

the sections following the table.

Table 2-23. Default PEG/DMI VT-d Remapping Engine Register Address Map (Sheet 1 of 2)

Address

Offset

Register

Symbol

Register Name

Reset Value

Access

0–3h

VER_REG

Version Register

0000_0010h

4–7h

RSVD

Reserved

8–Fh

CAP_REG

Capability Register

00C9_0080_

2066_0262h

10–17h

ECAP_REG

Extended Capability Register

0000_0000_

00F0_10DAh

RO-V, RO

18–1Bh

GCMD_REG

Global Command Register

0000_0000h

WO, RO

1C–1Fh

GSTS_REG

Global Status Register

0000_0000h

RO, RO-V

20–27h

RTADDR_REG

Root-Entry Table Address Register

0000_0000_

0000_0000h

28–2Fh

CCMD_REG

Context Command Register

0000_0000_

0000_0000h

RW-V, RW,

RO-V

30–33h

RSVD

Reserved

34–37h

FSTS_REG

Fault Status Register

0000_0000h

RW1CS,

ROS-V, RO

38–3Bh

FECTL_REG

Fault Event Control Register

8000_0000h

RW, RO-V

3C–3Fh

FEDATA_REG

Fault Event Data Register

0000_0000h

40–43h

FEADDR_REG

Fault Event Address Register

0000_0000h

44–47h

FEUADDR_REG

Fault Event Upper Address Register

0000_0000h

48–57h

RSVD

Reserved

58–5Fh

AFLOG_REG

Advanced Fault Log Register

0000_0000_

0000_0000h

60–63h

RSVD

Reserved

64–67h

PMEN_REG

Protected Memory Enable Register

0000_0000h

RW, RO-V

68–6Bh

PLMBASE_REG

Protected Low-Memory Base Register

0000_0000h

6C–6Fh

PLMLIMIT_REG

Protected Low-Memory Limit Register

0000_0000h

70–77h

PHMBASE_REG

Protected High-Memory Base Register

0000_0000_

0000_0000h

78–7Fh

PHMLIMIT_REG

Protected High-Memory Limit Register

0000_0000_

0000_0000h

80–87h

IQH_REG

Invalidation Queue Head Register

0000_0000_

0000_0000h

RO-V

88–8Fh

IQT_REG

Invalidation Queue Tail Register

0000_0000_

0000_0000h

RW-L

90–97h

IQA_REG

Invalidation Queue Address Register

0000_0000_

0000_0000h

RW-L

98–9Bh

RSVD

Reserved

9C–9Fh

ICS_REG

Invalidation Completion Status Register

0000_0000h

RW1CS

A0–A3h

IECTL_REG

Invalidation Event Control Register

8000_0000h

RW-L, RO-V

A4–A7h

IEDATA_REG

Invalidation Event Data Register

0000_0000h

RW-L