Intel G640T CM8062301002204 User Manual

Product codes
CM8062301002204
Page of 296
Processor Configuration Registers
266
Datasheet, Volume 2
2.21.2
CAP_REG—Capability Register
This register reports general remapping hardware capabilities.
B/D/F/Type:
0/0/0/VC0PREMAP
Address Offset:
8–Fh
Reset Value:
00C9_0080_2066_0262h
Access:
RO
Size:
64 bits
BIOS Optimal Default
000h
Bit
Attr
Reset 
Value
RST/
PWR
Description
63:56
RO
0h
Reserved
55
RO
1b
Uncore
DMA Read Draining (DRD)
0 = Hardware does Not support draining of DMA read requests.
1 = Hardware supports draining of DMA read requests.
54
RO
1b
Uncore
DMA Write Draining (DWD)
0 = Hardware does Not support draining of DMA write requests.
1 = Hardware supports draining of DMA write requests.
53:48
RO
001001b
Uncore
Maximum Address Mask Value (MAMV)
The value in this field indicates the maximum supported value for 
the Address Mask (AM) field in the Invalidation Address register 
(IVA_REG) and IOTLB Invalidation Descriptor (iotlb_inv_dsc).
This field is valid only when the PSI field in Capability register is 
reported as set.
47:40
RO
00000000b
Uncore
Number of Fault-recording Registers (NFR)
Number of fault recording registers is computed as N+1, where N 
is the value reported in this field.
Implementations must support at least one fault recording register 
(NFR = 0) for each remapping hardware unit in the platform.
The maximum number of fault recording registers per remapping 
hardware unit is 256.
39
RO
1b
Uncore
Page Selective Invalidation (PSI)
0 = Hardware supports only domain and global invalidates for 
IOTLB
1 = Hardware supports page selective, domain and global 
invalidates for IOTLB
Hardware implementations reporting this field as set are 
recommended to support a Maximum Address Mask Value (MAMV) 
value of at least 9.
38
RO
0h
Reserved
37:34
RO
0000b
Uncore
Super-Page Support (SPS)
This field indicates the super page sizes supported by hardware.
A value of 1 in any of these bits indicates the corresponding super-
page size is supported. The super-page sizes corresponding to 
various bit positions within this field are:
0h = 21-bit offset to page frame (2 MB)
1h = 30-bit offset to page frame (1 GB)
2h = 39-bit offset to page frame (512 GB)
3h = 48-bit offset to page frame (1 TB)
Hardware implementations supporting a specific super-page size 
must support all smaller super-page sizes (that is, only valid 
values for this field are 0001b, 0011b, 0111b, 1111b). 
33:24
RO
020h
Uncore
Fault-recording Register offset (FRO)
This field specifies the location to the first fault recording register 
relative to the register base address of this remapping hardware 
unit.
If the register base address is X, and the value reported in this 
field is Y, the address for the first fault recording register is 
calculated as X+(16*Y).