Intel G640T CM8062301002204 User Manual
Product codes
CM8062301002204
Datasheet, Volume 2
49
Processor Configuration Registers
2.5.3
PCICMD—PCI Command Register
Since Device 0 does not physically reside on PCI_A, many of the bits are not
implemented.
implemented.
B/D/F/Type:
0/0/0/PCI
Address Offset:
4–5h
Reset Value:
0006h
Access:
RO, RW
Size:
16 bits
BIOS Optimal Default
00h
Bit
Attr
Reset
Value
RST/
PWR
Description
15:10
RO
0h
Reserved
9
RO
0b
Uncore
Fast Back-to-Back Enable (FB2B)
This bit controls whether or not the master can do fast back-to-
This bit controls whether or not the master can do fast back-to-
back write. Since device 0 is strictly a target this bit is not
implemented and is hardwired to 0. Writes to this bit position have
no effect.
8
RW
0b
Uncore
SERR Enable (SERRE)
This bit is a global enable bit for Device 0 SERR messaging. The
This bit is a global enable bit for Device 0 SERR messaging. The
processor communicates the SERR condition by sending an SERR
message over DMI to the PCH.
1 = The processor is enabled to generate SERR messages over
DMI for specific Device 0 error conditions that are individually
enabled in the ERRCMD and DMIUEMSK registers. The error
status is reported in the ERRSTS, PCISTS, and DMIUEST
registers.
0 = The SERR message is not generated by the Host for Device 0.
This bit only controls SERR messaging for Device 0. Other
This bit only controls SERR messaging for Device 0. Other
integrated devices have their own SERRE bits to control error
reporting for error conditions occurring in each device. The control
bits are used in a logical OR manner to enable the SERR DMI
message mechanism.
0 = Device 0 SERR disabled
0 = Device 0 SERR disabled
1 = Device 0 SERR enabled
7
RO
0b
Uncore
Address/Data Stepping Enable (ADSTEP)
Address/data stepping is not implemented in the processor, and
Address/data stepping is not implemented in the processor, and
this bit is hardwired to 0. Writes to this bit position have no effect.
6
RW
0b
Uncore
Parity Error Enable (PERRE)
This bit controls whether or not the Master Data Parity Error bit in
This bit controls whether or not the Master Data Parity Error bit in
the PCI Status register can bet set.
0 = Disable. Master Data Parity Error bit in PCI Status register can
0 = Disable. Master Data Parity Error bit in PCI Status register can
NOT be set.
1 = Enable. Master Data Parity Error bit in PCI Status register CAN
be set.
5
RO
0b
Uncore
VGA Palette Snoop Enable (VGASNOOP)
The processor does not implement this bit and it is hardwired to a
The processor does not implement this bit and it is hardwired to a
0. Writes to this bit position have no effect.
4
RO
0b
Uncore
Memory Write and Invalidate Enable (MWIE)
The processor will never issue memory write and invalidate
The processor will never issue memory write and invalidate
commands. This bit is therefore hardwired to 0. Writes to this bit
position will have no effect.
3
RO
0h
Reserved
2
RO
1b
Uncore
Bus Master Enable (BME)
The processor is always enabled as a master on the backbone. This
The processor is always enabled as a master on the backbone. This
bit is hardwired to a 1. Writes to this bit position have no effect.